Superconducting nanowire single-photon detectors (SNSPDs) have emerged as leading cryogenic photon detectors, thanks to their high detection efficiency and low jitter. However, their large-scale integration remains limited by the wiring bottleneck between the cryogenic detectors and their room-temperature readout electronics. In applications such as color-center-based quantum computers (QCs), thousands of detectors may need to operate in parallel within a limited cryogenic cooling budget, thus asking for a scalable, low-power cryogenic electronic readout. To address these needs, this work introduces a cryogenic readout circuit directly wire-bonded to the SNSPD and using a high-impedance input to maximize the quality of the detector signal, thus relaxing the requirement of the cascaded amplifier and reducing its power consumption. An active quenching circuit is then adopted to ensure a reliable reset after the latching of the detector induced by such high input impedance. Implemented in 40-nm CMOS with an active area of <0.14 mm², the system achieves competitive performance at 0.1 K, delivering low timing jitter (<40 ps), high speed (dead time of ≈5 ns), and dark count rates (DCRs) below 1 Hz, while achieving a 5× reduction in power consumption (down to 20 μW) with respect to the cryogenic-readout state-of-the-art. Its ultralow-power operation and compact footprint make the proposed solution well-suited for integration within large-scale quantum-computing architectures.

This work presents a cryo-CMOS smart temperature sensor operating from room temperature down to 5 K. By adopting sensing elements (CMOS bulk diodes, pMOS/DTMOS in weak inversion) that circumvent the poor cryogenic performance of Si BJTs, a robust switched-capacitor second-order sigma–delta readout and cryogenic-aware design techniques, the sensor achieves a maximum error of ±0.73 K (four samples and two-point trim), a resolution below 0.05 K for a 102.4-ms readout duration, and a power consumption of 15.5 µW 93.5 µW) at 5 K (296 K).

Bluetooth Low Energy (BLE) powers large-scale Internet-of-Things networks but remains constrained by costly off-chip crystal oscillators. This work presents a 730 μW over-the-air frequency calibration technique that compares the energy of the upper and lower sidebands of a received BLE-compliant signal to calibrate the frequency accuracy of an on-chip LC oscillator from ±340 ppm to ±20 ppm within a 1.1 ms calibration period, while maintaining robust operation under a -23 dB signal-to-interference ratio at the adjacent channel.

This paper presents a scalable cryogenic readout solution for Superconducting Nanowire Single-Photon Detectors (SNSPDs) tailored for the readout of color-center-based qubits. The readout circuit, wire-bonded directly to the SNSPD, utilizes high input impedance to boost the signal amplitude, hence reducing the power consumption, and active quenching to prevent the latching induced by the high impedance. Fabricated in 40-nm CMOS in a 0.14-mm ² active area, the proposed system demonstrates competitive performance at 0.1 K, featuring low jitter [<60 ps Full Width at Half Maximum (FWHM)], high speed (dead time ≈ 5 ns) and low dark count rate (<1 Hz), while dissipating only 20 μ W. Such an ultra-low power and compact area enables the readout integration within a large-scale colorcenter quantum computer.

The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of dc bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this article presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryogenic CMOS (cryo-CMOS) demultiplexer and a cryo-CMOS dc digital-to-analog converter (DAC) have been developed in a 22-nm fin field-effect transistor process to control a codeveloped 2-D array designed with 648 single-hole transistors. Thanks to the dissipation below 120 µ W, the whole system operates at temperatures below 70 mK in a custom-built electrical/mechanical infrastructure embedded in a standard single-pulse-tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold structures, allowing to store 96 unique bias voltages over a 3 V range with a voltage drift between 60 µ V / s and 18 mV/s. This work demonstrates a tight integration at mK temperatures of cryo-CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors toward the large number of qubits required for a practical quantum computer.

This article presents a sub-7-GHz receiver (RX) for the fifth-generation (5G) local area base station applications. A Rauch transimpedance amplifier (TIA) with a third-order high-pass impedance in its feedback is adopted to enhance RX selectivity and provide higher loop gain (LG) at the bandwidth edge, improving in-band linearity for high-bandwidth applications. An N-path notch filter, sharing switches with down-converting passive mixers, is incorporated in the low-noise transconductance amplifier (LNTA) to enhance out-of-band linearity without limiting the RX’s operating frequency. Additionally, a frequency-dependent negative capacitance is realized at the LNTA input by exploiting the bandpass characteristic of the TIA input impedance, which helps achieve a flat in-band response, extend the RX bandwidth, and improve front-end filtering roll-off. Fabricated in 40-nm CMOS technology, the RX occupies a 1.3-mm² area, operates from 0.4 to 7.3 GHz, and consumes 105–195 mW from a 1.3-V supply. It achieves a third-order output third-order intercept point (OIP3) of 27–38 dBm over a 300-MHz channel bandwidth and a noise figure (NF) of 3.2–5.8 dB across its operating range. With its high linearity, low NF, and enhanced selectivity, the RX satisfies 3GPP standard requirements for reference sensitivity, in-band blocking, close-in blocking, and far-out blocking.

Quantum computers require large-scale error correction codes to circumvent the limited fidelity of physical qubits. However, current error decoders are either not scalable to practical code sizes or cannot meet the strict real-time decoding requirements. This work presents a novel decoder for stabilizer error correction codes that exploits hyperdimensional computing to offer an efficient hardware implementation for large-scale codes, thus achieving low latency and high throughput. Next to a universal approach for generating the necessary hypervectors, an efficient method specific to surface codes is devised. In this very first implementation, the proposed decoder outclasses popular graph-based decoders for small surface codes with depolarizing noise and efficiently scales to large codes, thus representing both a suitable solution for near-term real-time error correction and a promising alternative for future large-scale codes.