This paper proposes two fully passive techniques to reduce the supply sensitivity of an LC oscillator. An RC low-pass filter is employed to reduce the supply sensitivity of coarse-tuning switched capacitors stemming from code-dependent parasitic capacitance. To cancel the remaining supply sensitivity, the supply variations are scaled and coupled to polarity-switchable varactor pairs, which are introduced in the resonator to provide a frequency tuning gain that is reverse to the supply sensitivity. A programmable capacitive divider is used to scale the supply variations by a proper ratio. The proposed techniques are applied in a 5.83-6.99 GHz class-B LC oscillator. Prototyped in 65-nm CMOS, the oscillator occupies 0.24 mm ² and consumes 6.8 mW from 1 V. With supply perturbations in the 0.1-50 MHz frequency range, the measured reduction of the supply sensitivity is 20-46.2 dB, which is the highest reported over a wide frequency range. Benefiting from the fully passive implementation, the proposed techniques do not consume extra power or degrade the phase noise.

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.

Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).

This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range,fine-resolution DCO with only switchable metal capacitors. A third-harmonic boosting DCO simultaneously generates 22.5-28 GHz and sufficiently strong 68-84 GHz signals to satisfy short-range radar (SRR) and medium/long range radar (M/LRR) requirements. The 20.2 mW DCO emits -97 dBc/Hz at 1 MHz offset from 77 GHz,while fully satisfying metal density rules. It occupies 0.07 mm²,thus demonstrating both 43% power and 47% area reductions. The phase noise and FoM_T (figure-of-merit with tuning range) are improved by 1.8 dB and 0.2 dB,respectively,compared to state-of-the-art.

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.

In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail current and thus its oscillating amplitude. The parasitic capacitance of the active devices and correspondingly the oscillation frequency are stabilized in turn. A calibration loop is also integrated on-chip to automatically set the optimum replication gain that minimizes the variation of the oscillation amplitude. A 4.9-5.6-GHz oscillator is realized in 40-nm CMOS and occupies 0.23 mm² while consuming 0.8-1.3 mW across the tuning range (TR). The supply pushing is improved to <1 MHz/V resulting in a low <-49-dBc spur due to 0.5-12-MHz sinusoidal supply ripples as large as 50 mVpp. We experimentally verify the effectiveness of the proposed technique also in face of saw-tooth, multi-tone, and modulated supply ripples.

In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f ³ ) and thermal (1/f ² ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to 1/f ³ PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213-277-fs rms jitter in the 57.5-67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300-400 kHz.

Subharmonic residual in LO can degrade the performance of RF/mm-wave transceivers that employ frequency multipliers for LO generation. In this paper, we analyze the side effects that such subharmonics can cause. The effects are categorized to three parts: distortions in the up/down-converted signal, out-of-band emissions, and blocker tolerance in the receivers. A 60 GHz direct-conversion transceiver with a frequency tripler is taken for analysis. It is proved that there is no distortion or out-of-band emission issue with the presence of subharmonic in LO. For normal blocker tolerance requirements, the intrinsic subharmonic rejection capability in frequency multipliers is sufficient. In extreme cases, extra subharmonic filtering/rejection is needed.