A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

Journal article (2019)

Authors

Peng Chen University College Dublin
Feifei Zhang University College Dublin
Z. Zong Electronics - EEMCS , NXP Semiconductors
Suoping Hu University College Dublin
Teerachot Siriburanon University College Dublin
R.B. Staszewski University College Dublin
Research Group
Electronics (EEMCS) (TU Delft)
Copyright: © 2019 Peng Chen, Feifei Zhang, Z. Zong, Suoping Hu, Teerachot Siriburanon, R.B. Staszewski
DOI
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https://doi.org/10.1109/JSSC.2019.2939663
Digital-to-time converter (DTC) Phase-locked loop (PLL) Ultra-low power (ULP) Capacitor-based digital-to-analog converter (C-DAC) Constant slope Femtosecond resolution Integral nonlinearity (INL) Power-efficient
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Published Date

01-11-2019

Language

English

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.