To address the relentless increase in data rates in wireless communication systems employing advanced modulation schemes, such as 5G frequency range (FR) 2 [see Figure 1(a)], generating mm-wave signals with minimal integrated phase noise (PN) or RMS jitter is of paramount concern [1]. Figure 1(b) specifies the required jitter to achieve the targeted EVM performance. For instance, for an EVM of less than 3.5%, as needed by a 256-QAM 28-GHz carrier, the RMS jitter contributed by the LO must be below 200 fs. As the carrier frequency or the symbol constellation density increases, the required RMS jitter becomes even more stringent. For example, 1024 QAM at 39 GHz demands an RMS jitter of <50 fs [2], [3], [4].@en

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.

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This paper proposes a mm-wave quadrature frequency generator using injection-locked harmonic extractors (HEs) incorporated with quadrature class-F oscillators. While maintaining high output levels at 28 GHz, the utilization of injection locking technique improves the effective quality ($Q$)-factor and helps to achieve a fundamental harmonic suppression of 60 dB. This results in an FoM of the entire frequency generation system reaching -184 dB. The consideration of quadrature phase mismatch induced by electromagnetic coupling between quadrature buffers is also discussed.

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In modern transceivers, clock generation and planning is one of the key aspects. As a matter of fact, with the increasing occupation of the spectrum and with the increasing use of discrete front ends, non-idealities such as reciprocal mixing are getting more and more critical. This chapter presents the different techniques to enhance the performance of the clock generation especially for all-digital phase locked loops (PLLs) (ADPLLs).@en

This paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3- to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of -106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dBc/Hz at 27.3 GHz. Its flicker phase-noise (1/f³) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

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This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of -106 dBc/Hz [figure of merit (FoM) of -239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop.

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This paper presents a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic tank resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for shortest and well controlled common-mode current return path. Class-F operation with third-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10 GHz tank at the 30 GHz frequency generation while providing implicit divide-by-3 functionality. The proposed 27.3-31.2 GHz oscillator is implemented in 28-nm CMOS. It achieves phase noise of-106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dB at 27.3GHz. Its flicker phase-noise (1/f³) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

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This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.
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This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.@en