A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

Conference paper (2017)

Authors

Peng Chen University College Dublin
Feifei Zhang University College Dublin
Z. Zong Electronics - EEMCS
Hao Zheng University College Dublin
Teerachot Siriburanon University College Dublin
R.B. Staszewski University College Dublin
Research Group
Electronics (EEMCS) (TU Delft)
Low-power High resolution Low voltage Digital-to-time converter (DTC) PLL Constant slope Power-efficient Capacitor-based DAC (C-DAC) INL
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Published Date

2017

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.

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