Parasitic coupling between the building blocks within a fractional- N phase-locked loop (PLL) can result in noticeable spurs in its output spectrum, thus affecting the PLL’s usability in ultralow jitter applications. In this article, we focus on a chief contributor—“self-interference” caused by coupling from the PLL’s frequency-reference (FREF) clock buffer to the RF oscillator, while exploiting the fact that the resulting phase-disturbance pattern: 1) exhibits a sinusoidal shape and 2) is synchronized with the PLL’s output clock phase. Accordingly, we propose a digitally intensive pattern-aware approach to suppress the fundamental fractional spur raised by this self-interference mechanism. The proposed technique is applied to a fabricated digital PLL chip and reduces the worst spur level by 13 dB, thus proving its effectiveness.

In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce a new non-uniform clock compensation (NUCC) scheme to tackle an EVM degradation resulting from the beneficial use of a time-varying sampling clock that is re-timed to the phase-modulated carrier. We also employ a phase-domain digital predistortion (DPD) to combat the intrinsic non-linearity of an LC-type digitally controlled oscillator (DCO), thus avoiding the complications of frequency-dependent calibrations. The prototype, implemented in 40-nm CMOS, modulates the carrier in the range of 2.7-3.9 GHz from a 40-MHz reference. The measured EVM is -47 dB for a 60-Mb/s 64-PSK modulation under the case that the phase-modulated output is frequency-divided by K=8 , i.e., when the DCO exhibits the most significant non-linearity due to the large fractional FM bandwidth. When K=8 or 4, the measured EVM remains below -43 dB across the carrier-frequency tuning range and without re-calibrating the DCO non-linearity.

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.

We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre-distortion (DPD) and an encoding-assisted (EA)-LMS calibration. While generating a 10MHz 64-PSK signal, the prototype can achieve -46dB EVM with less than one-tenth of the calibration samples (time) required by the prior art.

This paper proposes a mm-wave quadrature frequency generator using injection-locked harmonic extractors (HEs) incorporated with quadrature class-F oscillators. While maintaining high output levels at 28 GHz, the utilization of injection locking technique improves the effective quality ($Q$)-factor and helps to achieve a fundamental harmonic suppression of 60 dB. This results in an FoM of the entire frequency generation system reaching -184 dB. The consideration of quadrature phase mismatch induced by electromagnetic coupling between quadrature buffers is also discussed.