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A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Journal Article (2023)
Author(s)

Zhong Gao (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Jingchu He (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Martin Fritz (Sony Europe Limited, Germany)

Yiyu Shen (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Zhirui Zong (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Gerd Spalink (Sony Europe Limited, Germany)

Morteza S. Alavi (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Robert Bogdan Staszewski (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Masoud Babaie (TU Delft - Electrical Engineering, Mathematics and Computer Science)

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Research Group
Electronics
DOI related publication
https://doi.org/10.1109/JSSC.2022.3209338 Final published version
More Info
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Publication Year
2023
Language
English
Research Group
Electronics
Issue number
6
Volume number
58
Pages (from-to)
1552-1571
Downloads counter
433
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Abstract

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.