A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Journal article (2023)

Authors

Z. Gao Electronics - EEMCS
J. He Electronics - EEMCS
Martin Fritz Sony Europe Limited, Germany
Y. Shen Electronics - EEMCS
Z. Zong Electronics - EEMCS
Gerd Spalink Sony Europe Limited, Germany
S.M. Alavi Electronics - EEMCS
R.B. Staszewski Electronics - EEMCS
M. Babaie Electronics - EEMCS
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Research Group
Electronics (EEMCS) (TU Delft)
Copyright: © 2023 Z. Gao, J. He, Martin Fritz, Y. Shen, Z. Zong, Gerd Spalink, S.M. Alavi, R.B. Staszewski, M. Babaie, More Authors
DOI
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https://doi.org/10.1109/JSSC.2022.3209338
Microelectronics Time-mode arithmetic unit (TAU) Phase-locked loop (PLL) Fractional spur Process voltage and temperature (PVT) Arithmetic Switches Clocks Digital-to-time converter (DTC) Phase locked loops Capacitors Voltage
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Published Date

2023

Language

English

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.