A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit
Z. Gao (TU Delft - Electronics)
Jinchu He (TU Delft - Electronics)
Martin Fritz (Sony Europe Limited, Germany)
Y. Shen (TU Delft - Electronics)
Z. Zong (TU Delft - Electronics)
Gerd Spalink (Sony Europe Limited, Germany)
Morteza S. Alavi (TU Delft - Electronics)
R.B. Staszewski (TU Delft - Electronics)
M. Babaie (TU Delft - Electronics)
G.B. Cavadini (External organisation)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.
help_outline