The final goal of this thesis is to figure out if it is possible to design an eight-band LTE antenna for <$0,20 with the same performance, quality and tunability as the current available eight-band LTE antennas. In the introduction the state of the art is presented where the most common currently available comparableantennas and modules are explored. Based on the state of the art, the requirements for the new antenna are set, consisting of a low band of 698-960MHz, a mid band of 1710-2170MHz and a high band of 2496-2690MHz. Based on this the solution is presented and finally 3 antennas are suggested.Antenna I shares the same mid and high band, but operates from 698-894 MHz, while antenna II operates from 805-960MHz due to limitation on the original antenna topology. The third antenna includes a meandered arm for the low band which adds a resonance peak at 960MHz and in this way the bands requirement is met. The antenna was synthesized in two designs and the second design stillneeds an experimental verification. It was concluded that with the given requirements it is possible to design an antenna for below $0,20, but a more in depth experimental verification is needed to check all the requirements.

In recent years, the demand for wireless communication devices is rapidly increasing and it is estimated to keep growing exponentially over the coming decade. This demand is accompanied by a demand for high-speed and reliable communication. One of the challenges faced by the RF design engineers is to fulfill these demands while utilizing the limited resource of the frequency spectrum to its full potential. High-bandwidth, multi-channel communication protocols are often used to address these requirements. Over the past decade, digital intensive transmitters are gaining popularity because of their suitability to be used with such protocols. This project addresses a requirement of a highly linear direct digital to RF modulator (DDRM) which fulfills the stringent adjacent channel leakage ratio (ACLR) and in-band linearity requirements of the modern communication standards. The main goal of this project is to design a low-power, highly linear DDRM with high modulation bandwidth that can provide an accurate reference signal to a high-power counterpart. This project presents a 2x11-bit, 4GHz digital-intensive I/Q interleaving DDRM with peak output power equal to 2dBm and maximum modulation bandwidth of 400MHz. The DDRM features a second order hold (SOH) interpolation filtering, digital pre-distortion-like unit cell configuration and complete digital CMOS based I/Q interleaving and mixing. The simulation results indicate that the DDRM achieves spurious free dynamic range lower than -50dBc in a 3.5GHz-4.5GHz band. Also the harmonic distortion (HD), intermodulation product (IM), counter-intermodulation (C-IM) products remain below -50dBc for a tone frequency of 400MHz. The entire design consumes 234mW of power. An additional harmonic rejection technique is evaluated which improves C-IM by 3dB-12dB.

The objective of the bachelor graduation project detailed in this thesis is the development of a system suited for testing radio frequency (RF) power amplifiers (PAs). This PA test system is in particular set up for testing two-transistor interpolating-supply amplifiers. Interpolating-supply PAs are efficiency-enhanced by employing multiple transistors supplied by different, fixed drain supply voltages, leading to different efficiency characteristics, which are then combined by switching between the transistors, resulting in an enchanced overal efficiciency. Turning on the right amplifying transistor takes place digitally by pre-adjusting the different data inputs or control of gate biases. The PA test system is required to provide support for measurement and signal generation for 40 dBm output power of a 20 dB gain PA. Moreover, it is required to provide remote control access to the measurement equipment and automation of the tests, implemented in MATLAB. The to-be-measured PA performance metrics were constrained to static tests for drain efficiency, power-added efficiency, AM/AM distortion, total harmonic distortion (THD) and intermodulation distortion (IMD). In order to meet the requirements while making use of the available resources, it was recognized that the following subsystems were necessary: • Baseband signal generation using a DAC; • RF signal generation using a to-be-calibrated IQ modulator; • Pre-amplifier, by own design; and • Spectrum analyzer, controlled remotely. The baseband signal generation subsystem was characterized with respect to noise and gain performance, which resulted in the making of noise-reducing LC low-pass filters. The provided IQ modulators were successfully calibrated for device non-idealities in an automated MATLAB GUI, allowing for clean RF signal generation. Three pre-amplifiers with over 27.5 dB power gain were realized for sufficient PA input power. A set of MATLAB functions and scripts for the spectrum analyzer and top-level control was written, enabling semi-automatic PA testing. At the time of writing this thesis, the PA test system was put in use to characterize and evaluate two interpolating supply PAs. For automation, another GUI was implemented for the PA test system. The system proved to be able to determine PA input, output and DC power to measure the gain, linearity and efficiency in multiple static tests and for different PA bias conditions. Also THD and IMD for single-transistor were measured using the PA test system. The results were to a realistic extent similar to the simulated PA characteristics, aside from some anomalies which could possibly be explained by PA design implementation mistakes or test system nonidealities.

In this bachelor thesis the design process of the audio and intermediate frequency amplifiers for a wireless FM tranceiver is documented and explained. The project was done using only descrete components for educational purposes.

This report describes the design of different amplifiers that are part of an FM transceiver. This is part of a larger project, which has the objective to design a complete FM transceiver from discrete components only, meaning that IC technology is not considered. The circuits designed are two baseband amplifiers, an intermediate frequency amplifier, a low noise amplifier and an RF power amplifier. The baseband amplifiers are implemented with a Darlington pair in common-collector configuration to achieve a high input resistance, low output resistance, and unity gain transfer. The intermediate frequency amplifier is centered at 9.95 MHz with a -3dB bandwidth of 2 MHz. The maximum gain is 40.5 dB and can be lowered with up to 39.7 dB using a potentiometer, based on the emitter degeneration principle. The low noise amplifier has a maximum noise figure of 1.4 dB over the RF carrier band of 88 to 108 MHz. It has a gain of 33 dB, and reaches its 1 dB compression point for an input of -33 dBm. The total harmonic distortion is less than 0.3%. A class E power amplifier is designed with an efficiency of 72.9%, a transmit power of 3.1 W, and a gain of 31.8 dB. Furthermore, this reports also presents a systematic design approach for amplifiers, which illustrate the core principles on which all the designs are based.

The "FM Chirp Waveform Generator and Detector for Radar" is a Bachelor graduation project with an educational purpose. In this thesis, two modules of the whole system are designed and simulated. In particular, the sawtooth generator and the FM detector. The sawtooth generator is used to generate a linearly increasing signal, which can be used to make a chirp signal. The FM detector is used to extract the original information signal from the received FM signal. The used procedure consisted of determining possible implementations, setting up the design equations, choosing component values and simulating the circuits in ADS. The sawtooth generator was implemented using a ramp generator, Schmitt trigger and a voltage clamper while the FM detector was implemented using a balanced slope detector and a differential-to-single-ended converter. The results showed that the sawtooth generator can successfully produce a sawtooth waveform and that the FM detector can successfully retrieve it. It was concluded that both the modules satisfy all the requirements, meaning that they should work as expected in the whole system. Finally, the future steps were listed which, among others, include improving the linearity of the sawtooth generator and the FM detector.

This thesis explains the design process of two subsystems of a radio transmitter and receiver. The goal of the project is to transmit audio over a distance using FM modulation. This report will focus on the power amplifier leading to the transmitting antenna and the low noise amplifier connected to the receiving antenna. A design process for a class E power amplifier and a low noise amplifier will be discussed.

This thesis presents the development of circuits and systems for fast wireline transceiver links that will enable a move towards highly integrable RF digital-to-analog converters. A new perspective on the analysis of bit error rates in wireline links leads to the PAM spectral design space chart: a novel, visual system design analysis tool for PAM wireline circuit designers. Moreover, a <2 mW/Gbps/lane, 10 Gbps wireline transmitter has been designed and taped-out in 40 nm CMOS. The proposed inherently pipelined 16:1 multiplexer and current mode logic driver design procedure are the key enablers for this performance. Finally, for development of a 10 Gbps wireline receiver, a novel self-synchronized receiver design is proposed that removes the need of a classical clock and data recovery loop. At its core, this receiver comprises the design of a high-speed two-tail comparator and an asynchronous metastability detection loop.

This report details the design and implementation of subsystems within a wireless FM transceiver. All the subsystems will be developed and integrated into a working FM transceiver. The subsystems discussed in this report are the modulator and demodulator. The modulator, on the transmitter side, varies the carrier wave frequency, based on the input audio signal. The demodulator, on the receiver side, can detect these variations and retrieve the audio signal. The modulator is implemented using a voltage controlled oscillator, which is based on the Colpitts oscillator. The input audio signal controls the oscillation frequency by modulating varicaps. The demodulator consists of mixer, amplifier and a slope detector. The amplifier is not discussed in this thesis. The mixer uses a local oscillator to shift the RF input signal to an intermediate frequency. This thesis proposes a mixer integrated into a local oscillator, using only one transistor. The detector is based on a slope detector, which differentiates the FM signal and converts it into an AM signal. The differentiator is implemented using a bandpass filter. The audio signal is retrieved from the AM signal using an envelope detector. The work will be concluded with a display of the complete FM transceiver circuit.

Recent advancements in Multiple-Input Multiple-Output (MIMO) radar techniques has created a paradigm shift in the overall radar technology to increase degrees of freedom in multi-function radar capabilities. The underlying principle of MIMO transmissions is to transmit independent waveforms from each antenna-element which do not interfere with other transmitted signals and establish wide illuminations which create multiple received signals back-scattered from the same target under observation to provide more information on the target aspects. One other principle is called colored transmission, by simultaneously radiating specific waveforms from each antenna-element/sub-array in different directions to achieve ‘space-time coding’. This can be explained as colored spatial distribution (multiple coded beams to probe the radar environment) instead of the white spatial distribution (single wide beam), such that the transmitted signals are now function of time as well as space. Recently, a novel multi-channel waveform agile demonstrator namely ASTAP (Advanced Space-Time Adaptive Processing) radar system has been designed and developed in Microwave Sensing, Signals and Systems (MS3) group. It consists of eight transmit channels with a single receive channel and hence can also be called as co-located Multiple-Input Single-Output (MISO) radar. The ASTAP radar system is capable of generating and transmitting independent waveforms via multi-channel Arbitrary Waveform Generator(AWG) simultaneously . However, the transmission of different coded waveforms with a radar system such as ASTAP demonstrator has some major challenges to be addressed first. These challenges include the impact of AWG on digital-domain generation of waveforms including limited-bits quantization errors, time- and phase-skew ( and/or jitter), influence of high-frequency up-conversion hardware components such as RF mixers (as non-linear devices) and antenna dispersion effects. First novelty of this thesis work is to investigate the influence of these system imperfections on waveform transmit ambiguity functions, waveform orthogonality in MISO transmissions, received signals separation and beamforming process for the synthesis of target azimuth distributions. It follows that an end-to-end system-level calibration to compensate these system imperfections on transmit side for different waveforms also serves as the second novelty of this thesis work and has been demonstrated with ASTAP radar system. For system performance analysis and beamforming applications, Over-the-Air (OTA) channel measurements have been done to compensate the ASTAP hardware distortions significantly and obtain the near-ideal waveform responses. Furthermore, it is investigated that to what extent it is possible to separate signals corresponding to each transmit channel from the composite received signal in a single receive channel. This study is extended further to generate and transmit two orthogonal beams occupying the same frequency band simultaneously and the corresponding transmit radiation patterns are recovered from the composite received signal matched filtering. Finally, conclusions along with future aspects and recommendations have been discussed.

This thesis presents two submodules which are part of 'an FM Chirp Waveform Generator and Detector for Radar', namely the mixer and the modulator. The goal of this project is to design and simulate these submodules from an educational perspective. The modulator is implemented as a single-ended common-base Colpitts oscillator with modulation capabilities added by means of varactor diodes. The carrier frequency of the presented modulator is tunable from 88 MHz to 108 MHz and the achieved modulation linearity for a sawtooth baseband signal is approximately 34 dB over the tuning range. The presented mixer consist of a double-balanced Gilbert-type topology with 29.5 dB (tunable) gain, 23 mW power consumption, high Input-Output isolation and single-ended output achieved by means of an active load. The project was carried out in the scope of the bachelor graduation project in the bachelor of electrical engineering at the Delft University of Technology.

This thesis describes the design of an ultra-low power temperature to digital converter. It is intended to monitor the excess heat produced during the wireless charging of implantable medical devices such as pacemakers. The TDC is designed to achieve an accuracy of ±0.1 °C (3 sigma) from 27 °C to 47 °C, and ±0.3 °C (3 sigma) from -40 °C to 85 °C after a 1-point trim. It also achieves a resolution of 0.01 °C at 10 Sa/s. The low power consumption (155 nW) is made possible by the implementation of a self-biasing BJT-core. Its low power consumption, accuracy, and resolution make it ideally suited for clinical temperature monitoring.

As the world is getting used to 5G technology, 6G is already on the horizon. With the ultimate goal of very low latency communication and Tbps data rates, 6G supports new wireless technologies such as virtual and augmented reality and autonomous driving. In this new generation of wireless communication, high frequencies up to 100 GHz are used which causes antenna arrays to shrink to the size of a post stamp. Antenna-in-Package (AiP) is an emerging technology that integrates these antennas directly in the packaging material of IC’s. This brings the benefit of high level of integration, making beamforming IC’s an all in one system for communications. Despite this, high integration also comes with challenges. These small antenna systems generate heat on a small footprint which emphasizes the need for a low-loss, efficient system. Moreover, free-space path loss is proportional to frequency so high radiated power is needed, further emphasizing the need for improved efficiency. Lastly, space inside the IC and package material is limited which requires compact solutions for the system’s components. Literature has shown that PA-antenna co-design can reduce losses at the PA-antenna interface by matching the antenna impedance to the impedance of the power amplifier, omitting the need for lossy impedance matching networks. This method, called direct impedance matching, has shown to improve power added efficiency (PAE) in antenna systems with single radiating elements and fixed linear arrays. Nevertheless, the advantage of direct impedance matching has not yet been demonstrated for phased array antennas with active beam forming/steering. This work demonstrates a novel analysis of PA-antenna co-design at 96 GHz using a 8x8 cavity-backed dual-polarized pin-fed stacked patch array. Two versions of this antenna array are designed in Ansys HFSS, one with an antenna impedance of 50 Ω, the benchmark, and one with a lower impedance of 25 Ω. Both designs are made on a custom package laminate stack-up and are compatible with pin-fed AiP technology. Using Keysight ADS, the antenna designs are co-simulated with an RF front-end circuit comprised of a single tone AC signal, ideal 1-64 channel power divider, ideal continuous phase shifters and realistic SiGe Class A cascode power amplifiers. In this setup, the 50 Ω reference antenna is connected to the PA’s with a matching network in between. Because the 25 Ω antenna array matches the optimal output impedance of the PA, it is directly connected. The performance of both antenna arrays are compared, with the focus on PAE and radiation characteristics. The results show that by going for a directly matched antenna the PAE of the system increases by 15.6% for a broadside beam and 30.4% with a scanned beam (θ = 45◦, φ = 45◦). EIRP for broadside and scanned beams increased from 50.3 W to 56.3 W and from 31.1 W to 37.9 W respectively. Bandwidth, gain, radiation efficiency and side-lobe levels were similar in both arrays but the 25 Ω antenna had 4 dB higher levels of cross-polarized radiation and a 4 dB stronger back-lobe behind the antenna. The advantage of higher efficiency and radiated power outweighs these drawbacks and makes direct impedance matching a good design strategy for 6G beamforming AiP technology.

Recent years have seen an exponential growth in required wireless data capacity. This exponential growth is expected to continue, while it is unsustainable if the power consumption associated with it will grow at the same rate. This calls for better power efficiency, which can usually be found in polar power amplifier architectures. This thesis focuses on the feasibility of a power RF-DAC, with as main focus to seek improvement in power efficiency. As all information up to the RF output is in the digital domain the design will be frequency agile, meaning that operation frequency is only dependent on the external matching network. As starting point an existing LDMOS technology is considered to implement a power Digital-to-RF-Amplitude Converter (DRAC) with a dedicated CMOS driver. As first demonstrator these two chips could be connected using flip-chip bonding. The proposed combination allows a maximum operation frequency of 3 GHz, providing a peak fundamental output power of 16,6 W with a drain efficiency of 64,4 % at the maximum operation frequency. Since the CMOS driver operates in Class-D a significantly lower average driver power consumption is expected compared to an analog system where a Class-A or Class-AB predriver would be used. This promising concept can change the way how future transmitters could be constructed. In conclusion a performance outlook will be given if a dedicated high power silicon technology that can feature the CMOS drivers would be available for 4G/5G applications.

In recent years, short-range reliable wireless system with high data rate and low power consumption has drawn sufficient attention and is in great demand in various applications. For biomedical implantable applications such as neural sensing and Brain-computer Interfaces (BCIs), due to the increasing number of sensing channels and elements, not only the precision of the biomedical analysis is increased, but also a wireless system with higher data rate is required. Besides the high data throughput, as an implanted device, settling within a human or animal body requires high reliability and low power consumption. Such a wireless system finds its position in smart wearable devices as well. With a higher data rate and small form factor, more functionalities can be adapted to those smart wearable devices. The energy-efficient characteristic also allows a longer working time and battery life. Similarly, the above-mentioned wireless system is a prime candidate for multi-media applications like virtual reality (VR). A higher data rate means more visual, audio, and sensing data can be transmitted simultaneously, which allows for more advanced functions and a better user experience. Furthermore, this high data rate, low-power wireless system can be also adopted at advanced control system. Among all possible technologies, Impulse Radio Ultra-Wide-Band (IR-UWB) technology is a promising solution for this short-range wireless system. Within this master thesis project, a transceiver exploiting IR-UWB technology is proposed and implemented as a solution for the above-mentioned short-range, high data-rate, low-power reliable wireless system. The transmitter is from Yu Huang’s hybrid modulation transmitter. A fifth-order wide-band low-power GM-C low-pass filter is implemented with novel closed-loop GM-C BiQuad architecture in the receiver. Besides, the adoption of Electrical Balanced Duplexer (EBD) and Digital Self-interference Cancellation (DSIC) promises strong isolation between transmitter and receiver. Thus, this transceiver is also full-duplex (FD) and achieves simultaneous radar and communication (RadCom). With RadCom, this transceiver accomplishes a higher integration level, higher spectral efficiency, and lower cost. Besides, it enables a newrange of applications since it can serve as a radar and communication device simultaneously. With the ability of ranging, object detection, and tracking, this transceiver is also an excellent solution for automotive sensing and human sensing: social distancing, child presence detection, non-contact vital sign detection, etc. Designed and fabricated in TSMC 28 nm CMOS process, this chip has a form factor of only 0.155 mm2. The achieved maximum data rate is 1.66 Gbps, while the transceiver DC power is within 20 mW.

Wireless data traffic is projected to steadily increase in the near future, necessitating the demand for transceivers with higher linearity and efficiency. Digital power amplifiers have the potential to achieve these higher efficiency demands while digital pre-distortion can be used to improve their linearity. Digital pre-distortion requires a highly-linear wideband observation receiver to down-convert and monitor the output of the transmitter. An observation receiver architecture that relies on baseband error-detection has been previously proposed by ELCA to reduce the stringent requirements on the analog-to-digital converter (ADC) in such an observation receiver. This thesis work presents a novel extremely-linear wideband voltage-domain harmonic-reject mixer targeting these observation receiver applications. The choice for a voltage-domain mixer instead of a current-domain mixer is first discussed. Three novel voltage-domain mixer topologies are then evaluated for their advantages and disadvantages, yielding the preferred topology for implementation. This circuit was designed in TSMC40nm thin-oxide CMOS technology yielding promising performance metrics when compared to similar state-of-the-art publications in the open literature; specifically in domain of observation receiver applications.

This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency. To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency.

The current trend in the state-of-the-art oscillators achieves low phase noise performance. Such stringent performance is demanded in modern Communication Systems. This thesis proposes the design of a CMOS oscillator achieving the ultra-low phase noise. This design is based on TSMC 40 nm technology, the supply voltage is 1.1 V, and the oscillation frequency is fstart=6.65 GHz and fstop=7.58 GHz, the tuning range is calculated to be 13 % with the Phase Noise@ 1 MHz(normalized to 10 GHz) varies from -128.1 dBc/Hz to -130.4 dBc/Hz and Figure of Merit varies from 188.0 dBc/Hz to 190.0 dBc/Hz, consuming average power of 95 mW and the fcorner is 250 kHz. Since the chip is still in fabrication and the final result only includes the simulation result. Further work involves the measurement and performance validation.