This thesis presents the development of a sensor fusion framework that integrates ultrasonic sensors with a rotating Light Detection and Ranging (LiDAR) system to generate an occupancy grid map. The objective is to improve spatial awareness for autonomous navigation by employing an adaptive LiDAR approach, wherein ultrasonic sensors are used to identify regions of interest for focused scanning.

The design and implementation of a test system are described, along with the development of an occupancy grid map capable of representing data from both LiDAR and ultrasonic sensors. To enhance the accuracy and reliability of the environmental representation, the occupancy grid map incorporates an inverse sensor model in combination with Bayesian statistical methods. ... Read more

This thesis presents the design, implementation, and evaluation of the RF (Radio Frequency) section of an Open-Hardware Vector Network Analyzer (VNA) intended for quantum research applications. The project aims to create a cost-effective, modular VNA system that fulfills the functional requirements necessary for qubit readout and other quantum measurements.
In the initial chapters, the overall architecture of the VNA is outlined, with specific attention to the power budget and system requirements. The RF generation principles are examined, and a range of RF generators are tested to ensure they meet the signal quality standards, such as spurious emissions and harmonic content. The performance of various RF mixers is also evaluated and found to be sufficient for the RF system.
Experimental results demonstrate the system’s capability to measure the S21 parameter of a resonator cavity, comparable to commercial VNAs. This validates that the RF system meets the specified requirements and can be effectively used in quantum research.
Future work suggested includes the measurement of generator frequency/phase stability over time and exploring the feasibility of implementing power sweeps to enhance the system’s functionality. The findings of this thesis contribute to the development of accessible and flexible tools for quantum technology research, promoting further advancements in the field. ... Read more

The focus of this report is the design and implementation of a universal gate driver for half-bridge circuits. This design includes a programmable dead-time controller and adjustable properties to ensure efficient and reliable switching on a variety of high-voltage applications. Furthermore, this work includes a comparative understanding of all design choices, such as the options considered for the dead-time controller, the gate driver component and the circuit of the output phase. The designed system is expected to receive as input a PWM signal and generate two output signals to drive a halfbridge configuration. The output pulses must be generated with a programmable dead-time and at the input switching frequency. The end product of this design will be used in the TU Delft Power Electronics Lab. The specific requirements are determined in order to meet the lab’s needs and this report further describes the process from acquiring the technical requirements, the circuit design, and finally, the prototype evaluation. ... Read more

As the world is getting used to 5G technology, 6G is already on the horizon. With the ultimate goal of very low latency communication and Tbps data rates, 6G supports new wireless technologies such as virtual and augmented reality and autonomous driving. In this new generation of wireless communication, high frequencies up to 100 GHz are used which causes antenna arrays to shrink to the size of a post stamp. Antenna-in-Package (AiP) is an emerging technology that integrates these antennas directly in the packaging material of IC’s. This brings the benefit of high level of integration, making beamforming IC’s an all in one system for communications. Despite this, high integration also comes with challenges. These small antenna systems generate heat on a small footprint which emphasizes the need for a low-loss, efficient system. Moreover, free-space path loss is proportional to frequency so high radiated power is needed, further emphasizing the need for improved efficiency. Lastly, space inside the IC and package material is limited which requires compact solutions for the system’s components. Literature has shown that PA-antenna co-design can reduce losses at the PA-antenna interface by matching the antenna impedance to the impedance of the power amplifier, omitting the need for lossy impedance matching networks. This method, called direct impedance matching, has shown to improve power added efficiency (PAE) in antenna systems with single radiating elements and fixed linear arrays. Nevertheless, the advantage of direct impedance matching has not yet been demonstrated for phased array antennas with active beam forming/steering.

This work demonstrates a novel analysis of PA-antenna co-design at 96 GHz using a 8x8 cavity-backed dual-polarized pin-fed stacked patch array. Two versions of this antenna array are designed in Ansys HFSS, one with an antenna impedance of 50 Ω, the benchmark, and one with a lower impedance of 25 Ω. Both designs are made on a custom package laminate stack-up and are compatible with pin-fed AiP technology. Using Keysight ADS, the antenna designs are co-simulated with an RF front-end circuit comprised of a single tone AC signal, ideal 1-64 channel power divider, ideal continuous phase shifters and realistic SiGe Class A cascode power amplifiers. In this setup, the 50 Ω reference antenna is connected to the PA’s with a matching network in between. Because the 25 Ω antenna array matches the optimal output impedance of the PA, it is directly connected. The performance of both antenna arrays are compared, with the focus on PAE and radiation characteristics. The results show that by going for a directly matched antenna the PAE of the system increases by 15.6% for a broadside beam and 30.4% with a scanned beam (θ = 45◦, φ = 45◦). EIRP for broadside and scanned beams increased from 50.3 W to 56.3 W and from 31.1 W to 37.9 W respectively. Bandwidth, gain, radiation efficiency and side-lobe levels were similar in both arrays but the 25 Ω antenna had 4 dB higher levels of cross-polarized radiation and a 4 dB stronger back-lobe behind the antenna. The advantage of higher efficiency and radiated power outweighs these drawbacks and makes direct impedance matching a good design strategy for 6G beamforming AiP technology. ... Read more

The growing demand for asynchronous data communication leads to a growing demand for CDR systems to recover the sampling clock of the received data. The DTC in the CDR system is the main jitter source of the recovered data. A low-jitter DTC is required to generate data of low-jitter performance, calling for the application of a phase noise filter. Currently, most phase noise filters are based on the charge injection technique, which can only filter the phase noise of the DLL-based DTC.

This thesis presents a new phase noise filter, which can filter both the DLL and PI phase noise. The proposed phase noise filter is inspired by the noise transfer function from the phase detector’s input to the delay locked loop(DLL) output of a type-II DLL, which shows a first-order low-pass transfer function. The noise suppression pole frequency is adjustable and can be modified by changing the
gain of each component in the circuit. In addition, by carefully placing the frequency of the LDO’s pole, second-order noise filtering can be realized.

During design, a 10-bit DTC is constructed first and the proposed filter is placed behind the DTC to verify the effectiveness of the filter. The design achieves the post-layout level. The simulation results show that the DTC’s phase noise drops from 1.099 psrms to 315.9 fsrms with the filter. The area is 695 μm × 693.5 μm. The design consumes 42.3 mW with 1.8V supply in 180nm BCD technology. ... Read more

This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency.
To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency. ... Read more

This thesis provides an investigation of the architecture and the design of the coarse DACs in continuous time pipeline (CTP) ADC to achieve high SFDR performance within a large bandwidth at sampling frequency of 4.8 GHz in TSMC 28nm technology.
Mismatch errors of the coarse DACs in CTP ADC are very critical as they introduce distortion and leak the quantization noise of the coarse stages to the output. Conventional calibration techniques such as dynamic element matching (DEM) linearize the DACs by converting the DAC distortion to white noise. However, after the linearization, the residual gain errors of the DACs remain. As a result, the quantization noise of the coarse quantizers leak to the output and degrade the performance of the CTP. Therefore, the residual gain errors of the DACs need to be estimated and calibrated. A resistive DAC architecture is proposed in the first stage of the CTP. The proposed architecture employs conventional DEM technique and is verified within the first stage of the CTP. 
Furthermore, two new innovative techniques are presented in this thesis. The first technique, advanced dynamic element matching (ADEM), translates both the distortion and the gain errors due to element mismatch of the DACs in multi-stage CTP ADC into white noise. The second technique, advanced data weighted averaging (ADWA), noise shapes both the the distortion and the gain errors of the DACs. Therefore, the presented techniques do not require additional digital calibration for element mismatch errors. Finally, a DAC architecture is presented that allows a feasible implementation of the presented techniques. The techniques are verified using simulations in MATLAB and Cadence. However, The presented techniques require the CTP stages to have equal impedances. ... Read more

Class-D amplifiers have gained popularity for their high-power efficiency, exceeding 90%. Among them, digital-input Class-D amplifiers stand out due to their superior integration and increased immunity to electromagnetic interference (EMI). This project introduces a high-performance digital-input Class-D amplifier, aiming for a dynamic range larger than 130 dB while maintaining total harmonic distortion (THD) at approximately -110 dB.

It employs a capacitive digital-to-analog converter (CDAC) to minimize noise. Mismatch in the CDAC is addressed through mismatch shaping techniques. Additionally, an open-loop transconductance stage is incorporated into the loop filter, enhancing dynamic range and striving for optimal performance. Extra paths are introduced in the loop filter to guarantee that amplifier swings are maintained within the designated range.
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Wireless data traffic is projected to steadily increase in the near future, necessitating the demand for transceivers with higher linearity and efficiency. Digital power amplifiers have the potential to achieve these higher efficiency demands while digital pre-distortion can be used to improve their linearity. Digital pre-distortion requires a highly-linear wideband observation receiver to down-convert and monitor the output of the transmitter. An observation receiver architecture that relies on baseband error-detection has been previously proposed by ELCA to reduce the stringent requirements on the analog-to-digital converter (ADC) in such an observation receiver. This thesis work presents a novel extremely-linear wideband voltage-domain harmonic-reject mixer targeting these observation receiver applications. The choice for a voltage-domain mixer instead of a current-domain mixer is first discussed. Three novel voltage-domain mixer topologies are then evaluated for their advantages and disadvantages, yielding the preferred topology for implementation. This circuit was designed in TSMC40nm thin-oxide CMOS technology yielding promising performance metrics when compared to similar state-of-the-art publications in the open literature; specifically in domain of observation receiver applications. ... Read more

The current generation of power management integrated circuits require fully integrated, low cost and low power solutions for voltage regulation. As final blocks in the internal power supply chain, excellent performance linear voltage regulators are required, especially in terms of dynamic response and stability. Since many voltage regulators are used, the chip area consumed by the regulators is a point of attention. Additionally, for some internal voltages the load current or capacitive loading is much lower, such that a scalable compact solution would be preferred. This project focuses on minimizing the on-chip area of voltage regulators while maximizing their performance.

The proposed design incorporates a novel circuit technique for improving the dynamic response of linear voltage regulators. In this thesis, the theory and analysis of current amplifier-based NMOST linear voltage regulators is introduced. In order to maximize the dynamic performance, multiple implementations are analyzed and their drawbacks are presented. Adaptive biasing has been implemented in order to improve the slew rate at the gate of the pass transistor and to increase the voltage loop gain bandwidth. The current loop is stabilized by means of bandwidth enhancement resistors, reaching a unity gain frequency of over 500MHz at maximum load current condition.

The linear voltage regulator occupies an area of 0.0078 mm2, consumes a quiescent current of 8.5µA and has a current capability of 10 mA. The circuit operates at supply levels varying between 7 to 18V, provides an output regulated voltage of 1.8V and is scalable in terms of the load capacitance and the load current. This design achieves a FOM of 0.613ps and is comparable to state-of-the-art designs. ... Read more

This thesis investigates the performance limits and design challenges of two current-mode front-end concepts that target WiFi and mm-wave 5G applications, respectively. The first concept is a power amplifier (PA), which operates at 2.4GHz and is driven by a direct-digital RF modulator (DDRM). A design for the PA, which also includes a parallel-combining transformer (PCT), was proposed, taped and tested in the QUBiC Gen8 technology of NXP Semiconductors. The measured results yield a peak output power of 27dBm, power efficiency of 20%, and an adjacent channel power ratio (ACPR) of -33.05dBc. In the other concept, the DDRM drives a power mixer (PMIX) which up-converts the DDRM signal to mm-wave frequencies. For the PMIX-based front-end, multiple linearity enhancement techniques were proposed and evaluated using simulations. For both current-mode front-end concepts, an extensive analysis on the theoretical output power and power efficiency limit was performed. Although current-mode operation has a high linearity potential, fully reaching this potential turns out not to be trivial, due to various device non-idealities and imperfect impedance matching. ... Read more

Biosensing has been developed rapidly for a number of biomedical applications, including neural monitoring, protein detection, bacteria detection and blood glucose monitoring. Among the branches of bio-sensing, capacitive sensing is a promising technique and utilized widely, since it is rapid, simple, label free and inexpensive. Compared with traditional capacitance sensing front end, capacitance to frequency (CFC) based frontend can be utilized to measure the capacitance change based on the frequency shift in the output. LC voltage-controlled oscillator (VCO) based CFC benefits from low power, low cost, high sensitivity, embedded wireless capability and miniaturized characterization, and it can be based on passive or active approaches. The limitation of cutting edge LC VCO based system is they are single channel. This thesis presents the design of a 3-by-3 400-MHz LC VCO based microsensor array for measuring bacteria concentration and related bio-analyte which behave capacitively in that frequency range. This would allow for high-resolution wireless capacitive sensing in a power-efficient way. The wireless capacitive microsensor array has been designed in a standard 0.18 um CMOS process. The sensor array is comprised of 3-by-3 pixels, and it is implemented by customized interdigitated capacitors. Each pixel has two customized 10.5 um * 10.5 um capacitors with 100fF capacitance value. A class-B VCO is implemented with 300fF buried metal-oxide metal (MOM) capacitor and 300nH off-chip inductor. The class-B oscillator converts the capacitance change in the sensor array into frequency shift and transmits the signal through wireless inductance link. The central frequency varies within ±3.3 MHz, with less than 1.4% RMS phase noise in process corners. By post-layout extraction, the circuit has 417 kHz/fF responsivity, 99.8% R^2 value and 1.5% RMS phase noise. Each pixel occupies and area of 30 um * 25 um area. In total, the whole front-end core circuit takes 140 um* 160 um chip area. This project contributes to further development of the multichannel LC VCO based sensing system, which could be utilized as a multi-channel low-power capacitance sensing technique in a long-term vision with combined detection and wireless transmission in the same front-end. ... Read more

In recent years, the demand for the wireless connectivity is increasing and leads to the research into the above 100GHz design. Developments have been made with the circuit and technologies to make the circuit operate at 100GHz. The current availability of silicon-based technologies providing devices with ft/fmax frequencies exceeding 300-GHz allows targeting above 100GHz for commercial telecom links.
The project presents an automated design approach that utilizes “Ocean” and “Skill” code to automate parts of the design flow of the mm-wave power amplifier. The Ocean script, the scripting language used by the cadence environment to control the simulations, together with Matlab is applied for data handling and to automate lots of the recurring simulations. The Skill-code, which under the cadence’s environment is applied to automatically generate the tunable layouts to realize a DRC conform circuit design.
The design of a 170-GHz Power Amplifier in 0.13-μm SiGe BiCMOS applied the automation design flow is presented in this thesis. The gain-stage characteristics such as gain, stability, power-added-efficiency, saturated output power or 1dB-Compression are automatically generated and plotted. Specifically, this 170-GHz PA achieves a 15dB power gain and 11.7dBm output 1dB compression point. ... Read more

This work presents a low-noise amplifier (LNA) for ultrasound imaging with built-in continuous time-gain compensation (TGC), which compensates for the time-dependent attenuation of the received echo signal and thus significantly reduces its dynamic range (DR). The proposed design combines the LNA and TGC functions in a single variable-gain current-to-current amplifier. Compared to conventional ultrasound front-ends, which implement the TGC function after an LNA that needs to handle the full DR of the echo signal, this approach can highly reduce the power consumption and the size. Compared to earlier programmable-gain LNAs with discrete gain steps, the continuous gain control avoids switching transients that may lead to imaging artefacts. The TGC function is realized by a novel feedback network consisting of a double differential pair that feeds a fraction of the output current back to the input. This fraction can be changed continuously using a control voltage that is applied to the gates of the differential pairs, to realize a gain range from -20 dB to +20 dB. To achieve an approximately constant closed-loop bandwidth in the presence of the changing feedback factor, a loop amplifier has been implemented whose gain is changed along with the feedback factor by dynamically changing its bias currents. This loop amplifier employs a current-reuse architecture to achieve high power-efficiency. In addition, a variable bias current source has been designed to appropriately bias the TGC feedback network. By employing a similar double differential pair topology as in the feedback network, this current source provides the required low noise at the highest gain setting and high current at the lowest gain setting within the available headroom. The LNA with built-in TGC function has been realized in 180nm CMOS technology. It has been optimized to interface with a 7.5 MHz CMUT transducer. Simulation results show that it achieves a 3dB bandwidth higher than 40 MHz across the full gain range. At the highest gain setting, its input current noise is 0.96 pA/sqrt(Hz). This leads to an input dynamic range of 93 dB, which is compressed into an output dynamic range of 53 dB by means of the 40 dB variable gain. The amplifier consumes 10.8 mW from a 1.8V supply, and occupies an estimated 302 x 320 um2 die area. ... Read more

Recent advancements in Multiple-Input Multiple-Output (MIMO) radar techniques has created a paradigm shift in the overall radar technology to increase degrees of freedom in multi-function radar capabilities. The underlying principle of MIMO transmissions is to transmit independent waveforms from each antenna-element which do not interfere with other transmitted signals and establish wide illuminations which create multiple received signals back-scattered from the same target under observation to provide more information on the target aspects. One other principle is called colored transmission, by simultaneously radiating specific waveforms from each antenna-element/sub-array in different directions to achieve ‘space-time coding’. This can be explained as colored spatial distribution (multiple coded beams to probe the radar environment) instead of the white spatial distribution (single wide beam), such that the transmitted signals are now function of time as well as space. Recently, a novel multi-channel waveform agile demonstrator namely ASTAP (Advanced Space-Time Adaptive Processing) radar system has been designed and developed in Microwave Sensing, Signals and Systems (MS3) group. It consists of eight transmit channels with a single receive channel and hence can also be called as co-located Multiple-Input Single-Output (MISO) radar. The ASTAP radar system is capable of generating and transmitting independent waveforms via multi-channel Arbitrary Waveform Generator(AWG) simultaneously . However, the transmission of different coded waveforms with a radar system such as ASTAP demonstrator has some major challenges to be addressed first. These challenges include the impact of AWG on digital-domain generation of waveforms including limited-bits quantization errors, time- and phase-skew ( and/or jitter), influence of high-frequency up-conversion hardware components such as RF mixers (as non-linear devices) and antenna dispersion effects. First novelty of this thesis work is to investigate the influence of these system imperfections on waveform transmit ambiguity functions, waveform orthogonality in MISO transmissions, received signals separation and beamforming process for the synthesis of target azimuth distributions. It follows that an end-to-end system-level calibration to compensate these system imperfections on transmit side for different waveforms also serves as the second novelty of this thesis work and has been demonstrated with ASTAP radar system. For system performance analysis and beamforming applications, Over-the-Air (OTA) channel measurements have been done to compensate the ASTAP hardware distortions significantly and obtain the near-ideal waveform responses. Furthermore, it is investigated that to what extent it is possible to separate signals corresponding to each transmit channel from the composite received signal in a single receive channel. This study is extended further to generate and transmit two orthogonal beams occupying the same frequency band simultaneously and the corresponding transmit radiation patterns are recovered from the composite received signal matched filtering. Finally, conclusions along with future aspects and recommendations have been discussed. ... Read more

This thesis describes the design of an ultra-low power temperature to digital converter. It is intended to monitor the excess heat produced during the wireless charging of implantable medical devices such as pacemakers. The TDC is designed to achieve an accuracy of ±0.1 °C (3 sigma) from 27 °C to 47 °C, and ±0.3 °C (3 sigma) from -40 °C to 85 °C after a 1-point trim. It also achieves a resolution of 0.01 °C at 10 Sa/s. The low power consumption (155 nW) is made possible by the implementation of a self-biasing BJT-core. Its low power consumption, accuracy, and resolution make it ideally suited for clinical temperature monitoring. ... Read more

This work describes a low-power and low-cost alternative to mechanical wind sensors, suitable for volume production in standard CMOS processes. The CMOS wind sensor operates in the electro-thermal domain; therefore, it has no moving parts and therefore requires very little maintenance. Moreover, the CMOS wind sensor is an active sensor, compared to its mechanical counterpart. Its sensitivity can be easily adjusted by changing the magnitude of the excitation signal.

Despite the manufacturing advantages of CMOS technology, the wind sensor has not attained commercial success in the market. This is due, in part, to process spread and packaging artifacts that have resulted in offset, nonlinearity and angle errors in detecting wind speed and direction. Because of this, expensive manual calibration is required to compensate these errors. Furthermore, its power consumption, in the order of tens of milliwatts, is not yet low enough to compete with its MEMS counterparts.

In this thesis, the design of a new version of the wind sensor is described, which aims to address the drawbacks of previous designs. Four extra resistors were added at each corner to electrically compensate for packaging artifacts, with the aim of reducing calibration costs. Larger thermopiles (a number of thermo- couples in series) were used, resulting in a greater signal-to-noise ratio (SNR). Internal signals were buffered to output pads to gain more insight into the magnitude of the sensor's internal signal swings. With these improvements, the resulting wind sensor chip consumes less than 30 mW of heating power and has an accuracy of ±0.6 m/s (speed) for wind speeds ranging from 1 to 25 m/s, and ±2.5°(direction) for a range of 4 to 25 m/s. ... Read more