The current generation of power management integrated circuits require fully integrated, low cost and low power solutions for voltage regulation. As final blocks in the internal power supply chain, excellent performance linear voltage regulators are required, especially in terms of dynamic response and stability. Since many voltage regulators are used, the chip area consumed by the regulators is a point of attention. Additionally, for some internal voltages the load current or capacitive loading is much lower, such that a scalable compact solution would be preferred. This project focuses on minimizing the on-chip area of voltage regulators while maximizing their performance.

The proposed design incorporates a novel circuit technique for improving the dynamic response of linear voltage regulators. In this thesis, the theory and analysis of current amplifier-based NMOST linear voltage regulators is introduced. In order to maximize the dynamic performance, multiple implementations are analyzed and their drawbacks are presented. Adaptive biasing has been implemented in order to improve the slew rate at the gate of the pass transistor and to increase the voltage loop gain bandwidth. The current loop is stabilized by means of bandwidth enhancement resistors, reaching a unity gain frequency of over 500MHz at maximum load current condition.

The linear voltage regulator occupies an area of 0.0078 mm2, consumes a quiescent current of 8.5µA and has a current capability of 10 mA. The circuit operates at supply levels varying between 7 to 18V, provides an output regulated voltage of 1.8V and is scalable in terms of the load capacitance and the load current. This design achieves a FOM of 0.613ps and is comparable to state-of-the-art designs.