The objective of the bachelor graduation project detailed in this thesis is the development of a system suited for testing radio frequency (RF) power amplifiers (PAs). This PA test system is in particular set up for testing two-transistor interpolating-supply amplifiers. Interpolating-supply PAs are efficiency-enhanced by employing multiple transistors supplied by different, fixed drain supply voltages, leading to different efficiency characteristics, which are then combined by switching between the transistors, resulting in an enchanced overal efficiciency. Turning on the right amplifying transistor takes place digitally by pre-adjusting the different data inputs or control of gate biases. The PA test system is required to provide support for measurement and signal generation for 40 dBm output power of a 20 dB gain PA. Moreover, it is required to provide remote control access to the measurement equipment and automation of the tests, implemented in MATLAB. The to-be-measured PA performance metrics were constrained to static tests for drain efficiency, power-added efficiency, AM/AM distortion, total harmonic distortion (THD) and intermodulation distortion (IMD). In order to meet the requirements while making use of the available resources, it was recognized that the following subsystems were necessary: • Baseband signal generation using a DAC; • RF signal generation using a to-be-calibrated IQ modulator; • Pre-amplifier, by own design; and • Spectrum analyzer, controlled remotely. The baseband signal generation subsystem was characterized with respect to noise and gain performance, which resulted in the making of noise-reducing LC low-pass filters. The provided IQ modulators were successfully calibrated for device non-idealities in an automated MATLAB GUI, allowing for clean RF signal generation. Three pre-amplifiers with over 27.5 dB power gain were realized for sufficient PA input power. A set of MATLAB functions and scripts for the spectrum analyzer and top-level control was written, enabling semi-automatic PA testing. At the time of writing this thesis, the PA test system was put in use to characterize and evaluate two interpolating supply PAs. For automation, another GUI was implemented for the PA test system. The system proved to be able to determine PA input, output and DC power to measure the gain, linearity and efficiency in multiple static tests and for different PA bias conditions. Also THD and IMD for single-transistor were measured using the PA test system. The results were to a realistic extent similar to the simulated PA characteristics, aside from some anomalies which could possibly be explained by PA design implementation mistakes or test system nonidealities.

The goal of the WiECG project is to create a prototype device that makes it possible to perform a 12-lead ECG measurement on patients without wires from the patient to a monitor. The solution consists of a transmitter and receiver, one of which is close or on the patients body and the other is connected to a monitor. This thesis describes the design and implementation of a subsystem of the prototype device that performs digitization, digital processing and reconstruction of the measured 12-lead ECG signal. This concerns converting nine 0 to 3.3V analog signals to the digital domain by using Analog-to-Digital converters, real-time filtering of nine signals with multiple digital IIR filters and reconstructing nine digital signals to the analog domain using Digital-to-Analog converters. Furthermore, component selection, design decisions and the implementation process will be detailed in this document. The subsystem proposed in this paper is able to successfully sample, efficiently filter and reconstruct nine signals in real time. Recommendations on improving the implementation to better adhere to the lower power requirements for a longer battery life are provided as future research prospects.

In the ADome project, a truncated icosahedron is used as a frame for multiple antenna nodes. These nodes are used to measure the radiation pattern of an antenna-under-test located in the center of this dome. Since these antennas can be placed anywhere in the ADome by the user, a calibration system is necessary to find the spherical coordinates of each of these antennas. In this thesis, a method is proposed that uses computer vision algorithms, written using the OpenCV library in C++, to locate each of these antennas by detecting controllable LEDs attached to the PCBs of the antenna nodes. The found pixel locations will then be used to get the spherical coordinates of the antennas with respect to the camera. Finally these spherical coordinates will be transformed to fit to the coordinate system of the ADome itself, by detecting landmarks in the form of fiducial markers which are located at predetermined locations. The methods of recognition of the antennas within using computer vision are discussed, implemented and tested on real and simulated data. The accuracy of finding the antennas on the real data was within 2 pixels from the true location. The methods regarding estimating the location of the antenna with respect to the camera are discussed next. These methods include a distortion estimation and correction, after which each pixel will get there corresponding spherical angles θ and φ. These methods are also tested on simulated and real data, where the accuracy on the real data falls within 0.5 degrees in comparison to the true data. Finally the methods of transforming the spherical angle θ and φ of the antenna with respect to the camera, to the coordinate system of the ADome are discussed. This starts with a method of recognizing fiducial landmarks (landmarks are accurately known reference points), where in this research there is chosen for ArUco fiducials. After this, the location of these landmarks can be used to determine the location and orientation of the camera within the ADome. The method of finding the distances between each of the landmarks and the camera, is discussed and tested and has an accuracy of 2 cm. The method of finding the location of the camera, and the method of finding the orientation of the camera are discussed, however this has not been tested and fully implemented yet. With this location and orientation the location of an antenna can be easily determined. In conclusion, this thesis is a good starting point for designing an Optical Calibration System, which could make determining the location of each of the antennas faster, and more accurate.

This thesis presents the development of circuits and systems for fast wireline transceiver links that will enable a move towards highly integrable RF digital-to-analog converters. A new perspective on the analysis of bit error rates in wireline links leads to the PAM spectral design space chart: a novel, visual system design analysis tool for PAM wireline circuit designers. Moreover, a <2 mW/Gbps/lane, 10 Gbps wireline transmitter has been designed and taped-out in 40 nm CMOS. The proposed inherently pipelined 16:1 multiplexer and current mode logic driver design procedure are the key enablers for this performance. Finally, for development of a 10 Gbps wireline receiver, a novel self-synchronized receiver design is proposed that removes the need of a classical clock and data recovery loop. At its core, this receiver comprises the design of a high-speed two-tail comparator and an asynchronous metastability detection loop.

As 5G is rapidly growing, wireless communication systems require wideband, compact and highly efficient power amplifier modules (PA) to drive the base station antenna arrays. Doherty PAs are implemented in most base stations. The final stage in these power amplifier modules has high supply voltages (28-50 V) to generate a high output power of >20 W at reasonable output impedance levels. This work replaces the ‘classical’ single-ended cascode PA to drive the Doherty PA, with a series push-pull (or totem-pole) PA to increase the efficiency and bandwidth of the driver. The series push pull designs can reach peak efficiencies of 70.7%, which is about 10 percentage points higher than the efficiency of the single-ended PA. To ensure that a fair comparison is made between the designs, the series push-pull designs operate at 5 V and 10 V supply, in order to generate an output voltage swing of 5 V and 10 V respectively. This is compared to the single-ended PA with a 5 V supply and 10 V output swing. Simulation results show that the series push-pull design does indeed increase the efficiency of the driver whilst having minimal AM-AM distortion (<1 dB) at the design frequency of 3.6 GHz.

The commercialization of millimeter wave frequencies for the 5G New Radio standard requires time and cost -effective testing equipment. The over-the-air measurement setup developed at the TU Delft (ADome) is able to reduce measurement time, by positioning multiple fixed sensing nodes around the antenna-under-test. To expand the system capabilities of the ADome, this work researches the possibilities of measuring signal quality by down-converting the high-frequency modulated signal to an intermediate frequency. This includes analysis on distributing the local oscillator to the sensing nodes, a proposed design and simulation of a passive single-balanced diode mixer circuit and simulated system EVM performance.

Recent years have seen an exponential growth in required wireless data capacity. This exponential growth is expected to continue, while it is unsustainable if the power consumption associated with it will grow at the same rate. This calls for better power efficiency, which can usually be found in polar power amplifier architectures. This thesis focuses on the feasibility of a power RF-DAC, with as main focus to seek improvement in power efficiency. As all information up to the RF output is in the digital domain the design will be frequency agile, meaning that operation frequency is only dependent on the external matching network. As starting point an existing LDMOS technology is considered to implement a power Digital-to-RF-Amplitude Converter (DRAC) with a dedicated CMOS driver. As first demonstrator these two chips could be connected using flip-chip bonding. The proposed combination allows a maximum operation frequency of 3 GHz, providing a peak fundamental output power of 16,6 W with a drain efficiency of 64,4 % at the maximum operation frequency. Since the CMOS driver operates in Class-D a significantly lower average driver power consumption is expected compared to an analog system where a Class-A or Class-AB predriver would be used. This promising concept can change the way how future transmitters could be constructed. In conclusion a performance outlook will be given if a dedicated high power silicon technology that can feature the CMOS drivers would be available for 4G/5G applications.

Receivers for millimeter-wave (mm-wave) 5G, with the ability to detect a low-power desired signal, in the vicinity of large power blockers, require highly linear circuitry with a large power consumption. Suppressing the out-of-band blockers reduces this power consumption. N-path filters (NPFs) have recently been used to reject interferers in adjacent channels, by using a tunable center frequency. The state-of-the-art NPFs at mm-wave, however, only have a limited attenuation or use a large chip area. In this thesis, a fourth-order NPF is designed for 26-30 GHz. The implemented filter combines two frequency-shifted NPFs to create a flat in-band response and a steep roll-off, without the use of a large passive baseband filter. A rejection of 14 dB in the center of the first adjacent channel is obtained. This increases up to 24 dB at far-out-of-band frequencies. The noise figure of 10-12 dB is the lowest of the state-of-the-art, due to the added low-noise amplifier (LNA) in front of the filter. Despite this LNA, the designed filter achieves a comparable power consumption (40 mW) and smaller area (0.2-0.3 µm) than the state-of-the-art. The filter designed in this thesis is the first reported active N-path filter at mm-wave. The bandwidth is among the smallest reported, while the estimated area is lower than the state-of-the-art.

Wireless data traffic is projected to steadily increase in the near future, necessitating the demand for transceivers with higher linearity and efficiency. Digital power amplifiers have the potential to achieve these higher efficiency demands while digital pre-distortion can be used to improve their linearity. Digital pre-distortion requires a highly-linear wideband observation receiver to down-convert and monitor the output of the transmitter. An observation receiver architecture that relies on baseband error-detection has been previously proposed by ELCA to reduce the stringent requirements on the analog-to-digital converter (ADC) in such an observation receiver. This thesis work presents a novel extremely-linear wideband voltage-domain harmonic-reject mixer targeting these observation receiver applications. The choice for a voltage-domain mixer instead of a current-domain mixer is first discussed. Three novel voltage-domain mixer topologies are then evaluated for their advantages and disadvantages, yielding the preferred topology for implementation. This circuit was designed in TSMC40nm thin-oxide CMOS technology yielding promising performance metrics when compared to similar state-of-the-art publications in the open literature; specifically in domain of observation receiver applications.

With the advancement of 5G/6G radio networks, the demand for high-performance power amplifiers (PAs) with clean spectra and compact constellations has increased significantly. To address these challenges, Artificial Intelligence (AI)-based digital predistortion (DPD) has emerged as a promising approach to linearize radio-frequency (RF) PAs. However, existing state-of-the-art AI-based architectures rely on computationally expensive online feature extraction to achieve satisfying linearization performance, resulting in complicated algorithm data paths and difficulty in energy-efficient hardware implementation. This thesis proposes a new deep recurrent neural network (RNN)-based DPD architecture, called Skip Gated Recurrent Unit (SGRU), with precise offline baseband signal feature extraction to bypass the need for complex online feature extraction while still maintaining high linearization performance. The proposed RNN architecture employs the end-to-end (E2E) learning framework to implement an efficient DPD model. By combining the offline feature extraction and E2E framework, we achieved a more streamlined and faster training method for wideband RF power amplifier (PA) DPD. With a simplified neural network architecture and fewer parameters, our approach utilizes 394 parameters to achieve an adjacent channel power ratio (ACPR) (lower/upper) of -45.16/-44.31 dBc for 100 MHz orthogonal frequency division multiplexing (OFDM) signal, ACPR (lower/upper) of -38.44/-42.09 dBc for 200 MHz OFDM signal. Compared to previous state-of-art phase gated just-another-network (PG-JANET) [1] and decomposed vector rotation just-another-network (DVR-JANET) [2], our approach has better ACPR and error vector magnitude (EVM) performance with parameters around 400. Compared to vector decomposition long-short-term memory (VDLSTM) [3], our approach achieves a better lower/upper band balance.

This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency. To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency.

Phase-locked loops (PLLs) are ubiquitous in many RF applications such as frequency synthesizers in wireline and wireless transceivers. In this project, a charge-sampling PLL has been designed, which employs a charge-domain sub-sampling phase detector. The high gain of the phase detector helps suppress the in-band phase noise, while the lowered duty cycle of the sampling reference clock results in reduced reference spurs. A current-starved ring oscillator has been designed to support an output frequency range of 1-2 GHz. In order to achieve the synthesis of fractional frequencies, a capacitive DAC based constant slope digital-to-time converter (DTC) has been designed. In order to calibrate the DTC gain (KDTC) over PVT variations, a digital background gain calibration loop has been introduced. The performance of the Fractional-N PLL is comparable to that of the state-of-the-art. In order to measure the PLL's performance in silicon, the design has been taped-out in TSMC 40-nm technology in July 2022.

The demand for faster mobile access and higher data throughput drives the evolution of wireless cellular communication, requiring larger modulation bandwidths and higher-order modulations and necessitating more efficient and flexible transmitter systems. Simultaneously, the advancements in nano-scale CMOS technologies have made transistors smaller and better suited for digital signal processing, with improved high-frequency performance for RF mixed-signal circuits. These advancements impact wireless RF transceivers creating the need to explore transmitter architectures beyond the level of the most established ones, which are exclusively analog up to date, by pushing them towards incorporating more digital circuitry. Consequently, the primary research question addressed in this is: “What are the potential performance advantages when the strength of (high-speed) digital CMOS is utilized within an RF front-end?” To answer this research question, this thesis proposes new architectures for digitalintensive transmitter line-ups. These architectures aim to enhance linearity, bandwidth, and power efficiency, and enable the full utilization of CMOS technology in digital operations within the RF front-end....@en

In this thesis, a new RF Power Amplifier design is proposed that targets for improving the efficiency profile of classical RF Amplifiers. This RF Power Amplifier is especially designed for modulation schemes that need a PA with high PAPR. The PA consists of two different stages that will be digitally controlled. One of these stages has an optimized efficiency profile for supporting input signals with nominal power and the other stage has an optimized efficiency profile for supporting input signals with peak power. The PA has been designed with GaN HEMT's which perform very well at high frequencies while delivering high power. The PA has been designed to perform optimally for frequencies around 100 MHz. Simulations show that at peak power, which is 40 dBm for this amplifier design, the PA has an efficiency of 63.5%. At 6 dB power back-off, the PA has an efficiency of 65.5%. The PA has a gain of approximately 20 dB at peak power level and approximately 18 dB at nominal power level. Furthermore the stability of the PA is optimized for the carrier frequency of the input signal. At 100 MHz the Rollet Stability Factor K is of magnitudes higher than unity which guarantees the stability of the circuit. Furthermore a PCB has been developed to do some investigations in how this new PA design will perform in practice. Measurements on this PCB show that in power back-off a maximum efficiency of 63% can be reached. Results of the performance at peak power show that the efficiency reaches a maximum level of 37%. A possible reason for this is insufficient suppression of undesired harmonics.

Many applications require wide bandwidth transmitters, but unfortunately, they usually have way less than 50% average drain efficiency for their modulated signals. This low efficiency is a significant drawback in all wireless applications, both for battery power devices and base stations. The Doherty radio frequency (RF) power amplifier architecture is widely used to enhance the average efficiency for modulated signals in base stations. Its popularity is due to its relatively cheap and simple hardware and its suitability to handle high-power wideband modulated signals. However, even Doherty amplifiers often have less than 50% average efficiency and are restricted in their RF bandwidth. This thesis reviews recent research on the Doherty power amplifier (DPA) topology and discusses possible power and bandwidth efficiency improvements. In the second part of the thesis, another topology is introduced, which also provides Doherty-like behavior. That topology is called a Pseudo Doherty Load Modulated Balanced Amplifier (PD-LMBA). The performance of PD-LMBA is compared with “conventional” DPAs. Circuit design examples of DPA and PD-LMBA are given. The thesis concludes with a PD-LMBA prototype design, which appears to be very promising in its wideband performance.

With the current advancements in quantum computing moving more circuitry into the cryogenic chamber there is a need for high-speed connectivity between the cryogenic and room temperature environment. Studies conducted to date have achieved high-speed links of multiple Gb/s utilizing a single CMOS chip at room temperature, yet a Cryo-CMOS wireline transmitter addresses a new topic in high-speed cryogenic electronic design necessary for the functioning and scale-up of quantum computers. This thesis entails the design of A DAC-based Cryo-CMOS 51.2 Gb/s PAM4 Wireline Transmitter. Overall, the proposed design is meant to demonstrate a high-speed signal generated by a Cyro-CMOS chip can be send through a cable from a cryogenic environment and received at room temperature. Requirements have been set up based on the measurement of the cable channel and simulation results showed these could be met with the designed circuitry. The system consists of a low-speed 16-to-1 serializing structure, a high-speed 4-to-1 Multiplexer, and a 6-bit (4b binary, 2b unary) CML DAC. The design is finished and taped out in 40-nm technology, however the chip is still in fabrication, so the results are based on simulation data only, in future research measurements will verify the working of the chip.

CMOS technology is one of the feasible solutions to meet the world’s growing demand for high data rates because it offers the prospect of SoC at a low cost. But, the PA forms the major bottleneck in making SoC because the PAs in high data rate wireless communication systems have the requirement of high-efficiency and good linearity even at backed-off power levels. Currently, PAs are mostly of classes A and B. Both of these are linear, but peak efficiencies are only 50% and 78% respectively. This thesis focuses on implementing Continuous Class F (CCF) PA for WiFi 802.11n over the bandwidth 2.1 - 2.7 GHz, which meets the requirement of high efficiency and good linearity even at backed-off power levels. The CCF PA overcomes Class F’s disadvantage of limited bandwidth as well as maintains peak efficiency of 90.7% over the entire bandwidth. The designed PA has four main blocks: the driver, inter-stage matching, output network, and output stage. The procedure to implement each of these blocks is explained extensively in chapters 3, 4, 5, and 6. The layout of the chip is carried out in TSMC 40 nm, and the chip size is 1.4 mm2. From simulations, the CCF PA has a maximum efficiency of 30 % and EVM of -25 dB at 3 dB back-off across the bandwidth 2.1 -2.7 GHz. The tapeout of the chip is planned in March 2021. Later, the chip can be tested and simulation results will be validated. To the best knowledge of the author, this is the first CCF chip at 2.4 GHz band.

This is an IR-UWB pulse generator design, which is based a switched-capacitor RF-DAC. This chip is taped out by Global Foundries 40nm CMOS LP process.

This thesis focuses on improving the readout of the ADome by implementing MCUs at each antenna probe, enabling local sampling and memory storage. The serial communication protocols CAN, SPI and I2C are considered and compared with one another. Ultimately, CAN is decided due to its robustness and simplicity which make the system cheap and ensures that the measurement will not get corrupted during transmission. Moreover, implementations of the new readout protocol are able to obtain measurement data store information at the local MCU. Test setups verification showed that antenna location can be stored and retrieved. Furthermore, the readout protocol is able to acquire multiple samples from the ADC locally.

N-path filters promise to miniaturize RF receivers by replacing various fixed off-chip filters with a single programmable on-chip filter. This research investigates some of the issues of receivers with N-path filters under strong blocker conditions: reciprocal mixing and inherent nonlinearity. First, a technique for reciprocal mixing cancellation is explored and shown to be impossible using only mixers and baseband impedances. Second, the inherent nonlinearity of both bandpass and notch N-path filters are simulated and modelled. To validate this approach, a highly linear receiver is proposed and designed in 40nm CMOS. The receiver has a bandpass common gate architecture, with a notch filter in the feedback path, improving linearity. The filter is isolated using buffers, improving LO leakage. The common gate stage is IM3 compensated to obtain good linearity (OOB IIP3 >20 dBm).