This article presents a reconfigurable millimeter-wave (mm-wave) fully integrated transceiver (TRX) front end that comprises a power amplifier (PA) and an integrated nonreciprocal ultra-compact isolator/circulator/receiver (RX). The circulator is based on a ring quarter-wave transmission line (QTL) topology with adjusted characteristic impedances, which improves transmitter (TX)-to-antenna insertion loss and TX-to-RX isolation. The circulator’s nonreciprocal gyrator features an and-gate switching-based N-path filter while also acting as a mixer-first RX. By activating the embedded cross-coupled negative resistors, the circulator can be reconfigured as an isolator. This compact N-path filter-based circulator/isolator occupies only 0.38 mm². Over a 27.1–31.1-GHz band, the realized front end offers >20-dB TX-to-RX isolation, with a measured TX-to-antenna insertion loss of 1.7 ⁓ 2.2 dB. The RX path tolerates the PA’s blocker signal, achieving 5-dBm in-band and 13-dBm out-of-band (OOB) B_1dB . The PA delivers 15.15-dBm peak output power with 33% drain efficiency. The functionality of the proposed frequency division duplex (FDD) front end is evaluated by simultaneous TX/RX operation with a 400-MHz TX/RX modulation bandwidth and 400-MHz channel spacing. The measured AM–PM of the realized PA with the integrated isolator shows relatively high voltage standing wave ratio (VSWR) resilience at the lower power level and less robustness against VSWR around its peak output power. The front-end prototype occupies only 0.7 mm², including circulator, PA, quadrature hybrid coupler LO generators, and baseband circuits.

This article introduces a 4 x 2 -way Doherty power amplifier (PA) tailored for millimeter-wave (mm-wave) 5G applications. It incorporates an advanced output combiner that consists of four differential 2-way Doherty networks, two quadrature hybrid couplers (QHCs), and a balun to enhance the output power P_out and improves power back-off (PBO) efficiency. Realized in 40 nm CMOS bulk technology with a core area of 1.54 mm², the prototype delivers a saturated power/peak gain surpassing 25.2 dBm/25.5 dB, and it demonstrates a drain efficiency (DE) exceeding 17.5%/10% at 0 dB/6 dB PBO across a 26–32 GHz band. The proposed mm-wave PA achieves error vector magnitude (EVM)/adjacent channel leakage ratio (ACLR) values of −25 dB/−33 dBc for a 2 GHz 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal with 9.6 dB PAPR, operating at an average output power (P_avg) of 11.3 dBm with an average drain efficiency (DE_avg) of 4% without using digital predistortion (DPD). For a 50 MHz 1024-QAM OFDM signal with 10 dB PAPR, it achieves a P_avg/DE_avg of 7.2 dBm/2% with EVM/ACLR of −35 dB/−42 dBc without DPD.

The increasing adoption of Deep Neural Network (DNN)-based Digital Pre-distortion (DPD) in modern communication systems necessitates efficient hardware implementations. This paper presents DPD-NeuralEngine, an ultra-fast, tiny-area, and power-efficient DPD accelerator based on a Gated Recurrent Unit (GRU) neural network (NN). Leveraging a co-designed software and hardware approach, our 22 nm CMOS implementation operates at 2 GHz, capable of processing I/Q signals up to 250 MSps. Experimental results demonstrate a throughput of 256.5 GOPS and power efficiency of 1.32 TOPS/W with DPD linearization performance measured in Adjacent Channel Power Ratio (ACPR) of -45.3 dBc and Error Vector Magnitude (EVM) of -39.8 dB. To our knowledge, this work represents the first AI-based DPD application-specific integrated circuit (ASIC) accelerator, achieving a power-area efficiency (PAE) of 6.6

Digital predistortion (DPD) is a popular technique to enhance signal quality in wideband radio frequency (RF) power amplifiers (PAs). With increasing bandwidth and data rates, DPD faces significant energy consumption challenges during deployment, contrasting with its efficiency goals. State-of-the-art DPD models rely on recurrent neural networks (RNNs), whose computational complexity hinders system efficiency. This letter introduces DeltaDPD, exploring the dynamic temporal sparsity of input signals and neuronal hidden states in RNNs for energy-efficient DPD, reducing arithmetic operations and memory accesses while preserving satisfactory linearization performance. Applying a TM3.1a 200 MHz-BW 256-QAM OFDM signal to a 3.5-GHz GaN Doherty RF PA, DeltaDPD achieves −50.03 dBc in adjacent channel power ratio (ACPR), −37.22dB in normalized mean square error (NMSE) and −38.52 dB in error vector magnitude (EVM) with 52% temporal sparsity, leading to a 1.8\times reduction in estimated inference power.

A wideband harmonic rejection (HR) voltage-domain mixer using resistive scaling is presented featuring excellent linearity and high intermediate frequency (IF) bandwidth. Thin-oxide devices with constant gate-to-source voltages (V_GS) are utilized to maximize the switching linearity. A novel switching core topology providing low-impedance IF outputs is proposed to support wideband in-phase (I) and quadrature (Q) mixer outputs when capacitively loaded by an analog-to-digital converter (ADC). Eight LO clock phases, each with a 25% duty cycle, are on-chip generated for quadrature down-conversion and HR. By cleverly activating and organizing the mixer branches, the mixer’s input impedance at radio frequency (RF) can be kept perfectly constant throughout all eight clock phases, enhancing the mixer’s linearity. The TSMC 40 nm-CMOS realized mixer reaches 20.9 dBm OIP3 at an IF of 50 MHz with a conversion loss of 22.5 dB. It offers an 800 MHz 3-dB IF bandwidth when connected to a differential capacitive loading of 0.15 pF, with a total power consumption of 40.7 mW drawn from a 1.1 V supply. The mixer targets linear wideband base station observation receiver applications.

Digital predistortion (DPD) is essential for mitigating nonlinearity in RF power amplifiers, particularly for wideband applications. This paper presents TCN-DPD, a parameter-efficient architecture based on temporal convolutional networks, integrating noncausal dilated convolutions with optimized activation functions. Evaluated on the OpenDPD framework with the DPA_200 MHz dataset, TCN-DPD achieves simulated ACPRs of -51.58 /-49.26dBc (L/R), EVM of -47.52 dB, and NMSE of -44.61 dB with 500 parameters and maintain superior linearization than prior models down to 200 parameters, making it promising for efficient wideband PA linearization.

With the rise in communication capacity, deep neural networks (DNN) for digital pre-distortion (DPD) to correct non-linearity in wideband power amplifiers (PAs) have become prominent. Yet, there is a void in open-source and measurement-setup-independent platforms for fast DPD exploration and objective DPD model comparison. This paper presents an open-source framework, OpenDPD, crafted in PyTorch, with an associated dataset for PA modeling and DPD learning. We introduce a Dense Gated Recurrent Unit (DGRU)-DPD, trained via a novel end-to-end learning architecture, outperforming previous DPD models on a digital PA (DPA) in the new digital transmitter (DTX) architecture with unconventional transfer characteristics compared to analog PAs. Measurements show our DGRU-DPD achieves an ACPR of -44.69/-44.47dBc and an EVM of -35.22dB for 200MHz OFDM signals. OpenDPD code, datasets and documentation are publicly available at https://github.com/lab-emi/OpenDPD

The RF performance of current-scaling digital transmitters (DTX) with polar, unsigned Cartesian, signed Cartesian, and multiphase architectures have been compared regarding power utilization of their output-stage switch banks and drain efficiency. The analysis includes various switch bank operation modes, such as switch bank sharing, segment activation interleaving, and their activation times (RF duty cycle of the segments). Current-scaling DTXs can be made compatible with high-power operations while offering high system efficiency and RF bandwidth. The average efficiency using Doherty power back-off efficiency enhancement is analyzed, and a comparison of the different proposed DTX implementations is presented.

This article introduces an N-way chain-weaver balanced power amplifier (PA) for millimeter-wave (mm-wave) phased-array transmitters (TXs). Taking advantage of the proposed combining network, an embedded impedance/power sensor is implemented, which can be utilized for output power regulation, built-in self-test, and load-based performance optimization. The proposed PA architecture offers linearity and gain robustness under the antenna's frequency/time-dependent voltage standing wave ratio (VSWR). In the event of impedance mismatch, the proposed PA provides N different loads equally distributed on the VSWR circle. Consequently, the performance of the PAs is the average of N PAs with N different loads, which makes this structure VSWR resilient. As a proof of concept, an eight-way chain-weaver balanced PA (BPA) is realized in 40-nm bulk CMOS technology, and it delivers 25.19-dBm P _SAT with 16.19% PAE. The proposed PA supports a 2-GHz 64-QAM OFDM signal with 16-dBm average power, achieving -25-dB error vector magnitude (EVM). The average EVM is better than -30.3 dB without digital pre-distortion (DPD) for an "800-MHz 256-QAM OFDM"signal while generating an average output power of 12.17 dBm. The performance of the PA is also evaluated under 1.5:1-3:1 VSWR conditions. The measured small-signal gain variation under VSWR 3:1 is ±0.7 dB. Moreover, assuming any frequency/time-dependent loading condition within the VSWR 3:1 circle, the proposed chain-weaver BPA achieves <2.8° amplitude-to-phase (AM-PM) over 3-GHz bandwidth. Besides, the embedded impedance/power sensor accuracy outperforms the state of the art. The proposed impedance sensor can measure VSWR 3:1 by the maximum angle and magnitude errors of 12.3° and 0.106, respectively.

Digital predistortion (DPD) enhances signal quality in wideband radio frequency (RF) power amplifiers (PAs). As signal bandwidths expand in modern radio systems, DPD's energy consumption increasingly impacts overall system efficiency. Deep neural networks (DNNs) offer promising advancements in DPD, yet their high complexity hinders their practical deployment. This article introduces open-source mixed-precision (MP) neural networks that employ quantized low-precision fixed-point parameters for energy-efficient DPD. This approach reduces computational complexity and memory footprint, thereby lowering power consumption without compromising linearization efficacy. Applied to a 160-MHz-BW 1024-QAM OFDM signal from a digital RF PA, MP-DPD gives no performance loss against 32-bit floating-point precision DPDs, while achieving -43.75 (L)/-45.27 (R) dBc in the adjacent channel power ratio (ACPR) and -38.72 dB in error vector magnitude (EVM). A 16-bit fixed-point-precision MP-DPD enables a 2.8× reduction in estimated inference power. The DPD code in PyTorch is publicly available on GitHub.

By introducing three different techniques, this article, for the first time, presents a wideband highly linear receiver (RX) capable of handling blocking scenarios in fifth-generation (5G) microcell base station applications. First, a parallel preselect filter is introduced to satisfy the base station co-location blocking requirements. Next, a combination of third-order RF and baseband (BB) filters is adopted to attenuate close-in blockers by a -120 dB/dec roll-off. Finally, a translational feedback network is proposed to reduce the in-band gain ripple to below 0.5 dB and provide better than -19 dB input matching. Fabricated in the 40-nm CMOS technology, the proposed RX occupies a core area of 0.8 mm2 and consumes 108-176 mW from a 1.3 V supply over the RX's 0.5-3-GHz operating frequency. It achieves a 3-dB bandwidth of 150 MHz and a noise figure (NF) of 2.6-3.9 dB over the RX frequency range. Activating the parallel preselect filter degrades the NF by as little as 1.2 dB in the worst case. The RX shows a ≥q 97.5% throughput when receiving a 100-MS/s quadrature phase shift keying (QPSK) signal with 7.5-dB SNR and achieves a -9.7 dB error vector magnitude (EVM) while facing a -15 dBm continuous-wave (CW) blocker only 20 MHz away from the desired 100-MS/s QPSK signal with 12.3-dB SNR, thus satisfying the 3rd generation partnership project (3GPP) requirements with sufficient margin.

This article presents a wideband, energy-efficient digital transmitter (DTX) suitable for multi-mode/multi-band wireless communication applications. It features various operation modes comprising Cartesian (Modes-1/-2) and multi-phase (Modes-3/-4) configurations utilizing LO clocks with different duty cycle in the interleaving/non-interleaving configurations. The multi-phase operation compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with a 45° relative phase difference and a 3-bit phase selector scheme. The different operation modes are extensively analyzed and compared. Fabricated in a 40-nm CMOS process with an off-chip matching network, the proposed DTX occupies a core area of 0.72 mm2 and delivers 23.18-dBm RF peak power at 2.1 GHz from a 0.95-V supply voltage with drain/system efficiencies of 66.26%/52.59%, respectively. Utilizing a simple memory-less digital pre-distortion (DPD) for a 160-MHz four-channel 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal, the DTX delivers an average P Out of 13.5/11.4/7.7/9.4 dBm, achieving an adjacent channel (power) ratio (ACL(P)R) of better than -42/-40/-40/-38 dBc and an average error vector magnitude (EVM) of -36/-34/-34/-32 dB, operating in Modes-1/-2/-3/-4, respectively. While transmitting a 200-MHz single-channel 256 (1024)-QAM OFDM signal at 2.4 GHz in Modes-1/-4, the average delivered output power is 14.11/9.29 (12.23/7.32) dBm with average drain and system efficiencies of 33.17%/26.3% (23.82%/22.83%) and 24.81%/22.85% (19.34%/18.81%), while the ACLR and EVM are better than -42/-41 (-43/-43) dBc and -34.6/-33.1 (-33.5/-33.9) dB, respectively.

This paper presents an advanced yet simple digital pre-distortion (DPD) technique for digital I/Q transmitters (DTXs). Exploiting the I/Q orthogonality, an effective 2×1-D DPD procedure is proposed to bypass the exhaustive 2-D search of the entire constellation diagram. Utilizing this technique, a four-way Doherty DTX is linearized. Measurement results demonstrate that for a non-contiguous six-carrier OFDM-QAM signal with aggregated bandwidth of 150MHz, the ACPR is better than -47.3dBc, and EVM is better than -41/-40dB for channel-1/-6, respectively.

This paper proposes a power amplifier (PA) correction technique to recover from load mismatch. It utilizes a main PA, two auxiliary PAs, and a coupler. By adjusting the input drive levels of the PAs it can recover the output power and to a great extent the efficiency of the main PA even when exposed to 2:1 VSWR mismatch conditions. When connected to 50O loading, only the main PA is active, for impedances below or above 50 O, besides the main amplifier, one of the auxiliary PAs is also activated. The power generated by the auxiliary PA adds in phase to the output power of the main PA, as such allowing the output power to be constant at the expense of a minor efficiency penalty.

This paper presents a 40nm CMOS mm-wave 3-way Doherty power amplifier (PA) suitable for 5G mm-wave transmitters. It features a bandwidth-enhanced technique using a compact single-supply balun-first 3-way Doherty combiner. The realized front-end with a core area of 0.77 mm2delivers a peak power/gain of more than 20 dBm/16 dB and a drain efficiency (DE) of better than 15 %/22 %/33 % at 9.5 dB/6 dB/0 dB power back-off across a 24-to-30 GHz band. At 26 GHz, it achieves an EVM/ACLR of -23.5 dB/-29.5 dBc for an 800MHz 64-OFDM signal with 9.8 dBm average output power and a 15 % average DE.

A current-mode direct-digital RF modulator (DDRM)-based transmitter (TX) architecture is proposed in this article for energy-efficient wireless applications. To demonstrate its key principles, a 2×13 bit demonstrator is implemented in a 40-nm CMOS technology. This DDRM can operate standalone or as a driver for a common-gate (CG)/common-base (CB) power amplifier (PA). The proposed DDRM is based on current-steering radio frequency digital-to-analog converters (RFDACs) that feature an extra current division path to allow the generation of the optimum current-mode class-B drive profile for the final CG/CB PA, facilitating energy-efficient TX operation without compromising linearity. For this purpose, the DDRM uses signed-IQ mapping combined with a class-B harmonic rejection (HR) technique. In addition, an advanced dynamic biasing technique is introduced to further enhance the TX line-up efficiency in deep power back-off (PBO) region. The DDRM driver standalone can provide 19.6-dBm RF peak output power. It supports a '160-MHz 256-QAM' signal at 2.4 GHz with an adjacent channel leakage ratio (ACLR) of -40.3 dBc and an error vector magnitude (EVM) of -33 dB, without using any digital pre-distortion (DPD). When connected to a CB SiGe PA, the overall TX line-up achieves an output power of 27 dBm and an overall TX system efficiency of 20%. This DPD-free TX line-up achieves an ACLR of -37.7 dBc and an EVM of -30 dB, respectively, when operating with an '80-MHz 64-QAM' signal at 2.2 GHz.

This article presents a wideband blocker tolerant receiver (RX) for fifth-generation (5G) user equipment applications. Two programmable zeros around the channel bandwidth are introduced to sufficiently suppress the close-in blockers of 5G applications. Since the effect of zeros gradually diminishes at larger out-of-band offset frequencies, an auxiliary current-sinking path is also introduced to reduce the RX input impedance at far-out offset frequencies. Moreover, a simple second-order transimpedance amplifier (TIA) is adopted to enhance the proposed RX selectivity. The utilized TIA synthesizes two complex conjugate poles to achieve a flat gain response and -40 dB/dec roll-off. A 40-nm CMOS RX prototype occupies 1.15mm2 and consumes 84-140mW from a 1.3-V supply voltage over the 0.5-3-GHz operating frequency range. The RX achieves a 160-MHz RF bandwidth, 2.6-4.2-dB noise figure, a -0.3-dBm blocker 1-dB compression point (B1dB), and an out-of-band third-order intercept point (IIP3) of 22.5 dBm. As a test case, using the 3GPP standard, a -15-dBm continuous wave (CW) close-in out-of-band blocker located at 85-MHz offset from the passband edges is applied to the RX. Thanks to the receiver's high selectivity, the RX achieves 100% throughput while detecting 100-MS/s quadrature phase shift keying (QPSK) signal with 16 dB higher power than the reference sensitivity.