This thesis presents the design of a bidirectional low-dropout voltage regulator(LDO) for CMOS drivers in a 3.5 GHz digital transmitter (DTX). A tightly regulated 0.9V mid-rail supply is required to ensure short rise/fall times and maintain Adjacent channel leakage ratio(ACLR) performance. Regulator specifications were derived by porting the LDMOS driver to a 22 nm FDSOI process and characterizing its current demand across PVT corners, requiring up to 2.9 mA sourcing and 1.9 mA sinking with < ±1.5 mV voltage deviation. A complementary push–pull architecture with a folded-cascode error amplifier, super-source-follower buffers, and differentiator-based compensation was implemented to achieve low output impedance without excessive on-chip capacitance. Simulations confirm < 573 μA quiescent current, phase margin > 45°, and acceptable ACLR performance, validating the design for integration in CMOS/LDMOS DTX systems.

Digital pre-distortion (DPD) is a well-established and highly effective technique for linearizing radio frequency power amplifiers. With the advent of 5.5G/6G base stations and Wi-Fi 7, DPD has become increasingly critical to support wideband signals and higher data rates. State-of-the-art DPD models predominantly leverage neural networks to process time-domain (TD) signals. While the TD-DPD enables point-to-point pre-distortion of TD signals, frequency-domain (FD) DPD requires the entire spectrum as input to generate time-domain outputs. This requirement results in a large number of input neurons and significantly increases computational complexity, thereby limiting the practical application of FD-DPD and hindering insights into frequency-dependent distortion characteristics. This paper introduces a lightweight frequency-domain (FD) neural network architecture incorporating a novel feature extraction method and integrate it with a TD-DPD model to develop an innovative Hybrid-DPD model. Evaluated on the OpenDPD platform with DPA_200MHz dataset, the Hybrid-DPD achieves simulated ACPR of -50.28 dBc, EVM of -45.30 dB and NMSE of -42.92 dB with 578 parameters. This performance surpasses that of the time-domain-only DPD with a comparable parameter count of486 by approximately 1 dB.

As a crucial component, one common challenge of power amplifiers (PA) is the nonlinearity in the wireless communication system. Digital predistortion (DPD) is essential for mitigating nonlinearity in radio frequency (RF) power amplifiers, particularly for wideband applications. This thesis work aims to present the TCN-DPD model, a novel parameter-efficient architecture based on temporal convolutional networks (TCNs) to enhance the performance of PA. Therefore, the main problem should focused on the TCN-DPD model implementation with parameter efficiency. When TCN architecture was designed with several noncausal and dilated depthwise convolution layers and 1*1 convolution layers, optimized activation functions should be explored to complete the TCN architecture. By evaluating on the OpenDPD framework with the DPA_200MHz dataset, Hardswish, Tanh, SiLU, and GELU were considered by benchmarking different activations of TCN-DPD based on SIM- NMSE and SIM-ACLR metrics on average. Hardswish was confirmed in the later experiments as the optimized activation function in TCN architecture based on simulated results ACLR of -51.54 dBc and
NMSE of -44.61 dB. Since the TCN-DPD architecture was completed, this proposed model’s performance in PA and DPD benchmarks is desirable to be tested, and later experiments will use the same dataset and framework as the benchmark of activation function did. In PA benchmarking, the TCN model achieves SIM-NMSE -34.99 dB on average compared to other models, LSTM, GRU, RVTDCNN, VDLSTM, PNTDNN, and DGRU. This achievement shows the TCN architecture has a high potential to handle a range of dependencies efficiently in the DPD application system. Furthermore, DPD benchmarking is the main experiment in this thesis. Two architectures were selected as the pre-trained PA model: the DGRU and TCN models. When the pre-trained PA is fixed as the DGRU model, TCN-DPD demonstrates superior linearization performance with only 500 real-valued parameters, achieving averaged and simulated ACPRs of -51.58/-49.26 dBc (L/R), EVM of -47.52 dB, and NMSE of -44.61dB. The results are simulated ACPRs of -50.39/-50.01 dBc (L/R), EVM of -47.88 dB, and NMSE of -45.51 dB in average when the pre-trained PA model is TCN. Both DPD benchmarks include different DNN-DPD models, and TCN-DPD has superior performance in the comparison, especially the SIM-NMSE and SIM-EVM performance is significantly higher than other models when the pre-trained model is TCN. These results establish TCN-DPD as a promising solution for efficient wideband PA linearization. Moreover, the evaluation extended to DNN-DPD performance with various numbers of parameters ranging from 200 to 1000, where the TCN-200 model highlighted its effectiveness by showing impressive results in SIM-NMSE -41.27dB/-43.51dB(DGRU/TCN PA), achieving superior linearization performance while using significantly fewer parameters than existing deep neural network solutions, proving the TCN-DPD model’s parameters efficiency.
The research in this thesis conclusively demonstrates that TCNs can be implemented in DPD applications, providing more parameters efficiency, better performance, and robust PA linearization solutions, potentially setting a new alternative in DPD technology.

To meet the growing demand for higher data rates, the fifth generation (5G) of mobile communication has been introduced for low-band, mid-band, and high-band frequencies. In 5G applications, higher bandwidth and complex modulation schemes are employed for this purpose.

To mitigate the high path loss associated with mm-wave frequencies, greater focus has been placed on low-band and mid-band radios. Even the operating frequency of sub-6GHz radios has been extended to sub-7GHz. However, the congested sub-7GHz spectrum has kept the offset frequency of close-in blockers constant compared to the previous standards, such as 4G. This imposes stringent requirements on receiver (RX) selectivity and linearity.

This thesis presents reconfigurable wideband low noise transconductance amplifier (LNTA)-based RXs for sub-7GHz radios. The proposed RXs have high bandwidth and decent noise figure (NF) performance to employ highorder modulation schemes and achieve a high data rate. This thesis introduces techniques to enhance the RX selectivity for suppressing the close-in blockers of 5G user equipment, microcell base station, and local area base station applications. Moreover, this thesis proposes RXs with decent far-out out-ofband linearity for base station co-location applications where strong blockers are present from other standards.

Chapter 1 outlines the evolution of wireless communication leading to 5G applications. It introduces the 5G standard and highlights its stringent requirements on RX operating frequency, bandwidth, noise figure, and linearity. Following a brief discussion on N-path filters and their role in enabling wideband RXs, Chapter 1 reviews state-of-the-art RX designs and identifies their limitations for 5G applications. Finally, it defines the objectives and scope of this thesis.

Chapter 2 targets 5G user equipment applications and introduces a wideband blocker tolerant receiver fabricated in 40-nm bulk CMOS technology. By incorporating programmable zeros and a second-order transimpedance amplifier (TIA), the RX achieves enhanced selectivity and fulfills the stringent linearity requirements of 5G for close-in blockers. An auxiliary path is employed to reduce the RX input impedance at far-out offset frequencies, creating a current-sinking path for far-out blockers. In this way, the proposed RX achieves decent out-ofband linearity performance. To determine the component values for both the RF front-end and the second-order TIA, two design guides are developed based on the 5G standard. The proposed RX successfully meets 5G requirements for reference sensitivity and out-of-band blocking tests.

Chapter 3 presents a wideband RX for 5G microcell base station applications. This Chapter targets microcell co-location scenarios. Hence, it adopts a parallel preselect filter to achieve decent far-out out-of-band B1dB. Third-order RF and baseband filters deliver sixth-order channel selectivity to handle close-in blockers of base station applications, where the ratio of blocker offset frequency to RX bandwidth is 1/10. Additionally, a translational feedback network provides input matching and minimizes in-band gain ripple to below 0.5 dB. The RX’s reconfigurable architecture supports a low-noise mode and linear mode. Leveraging its current-mode operation and sharp filtering, the implemented RX in 40-nm CMOS technology complies with all 3GPP requirements for reference sensitivity, in-band blocking, and out-of-band blocking.

Chapter 4 introduces a wideband LNTA-based RX for 5G local area base station applications. The proposed RX covers both low- and mid-band frequencies. Firstly, this Chapter determines the optimal TIA architecture for 5G applications. To do so, the first-order and Rauch TIAs were thoroughly analyzed and compared in terms of transfer function, input impedance, loop gain, and noise performance. The Rauch TIA was selected for its superior selectivity and higher loop gain for out-of-band signals, with additional selectivity enhancement by adopting a third-order high-pass filter integrated in parallel with the TIA feedback resistor. The RX incorporates the Rauch TIAs with passive mixers and an LNTA featuring an N-path notch filter in its feedback. To enhance the RX’s operating frequency range, two switch sets at the LNTA output (one for the N-path notch filter and another for the down-converting mixers) were merged. Furthermore, the band-pass characteristic of the TIA input impedance is leveraged to introduce positive feedback in the LNTA, increasing the 3-dB bandwidth without compromising out-of-band rejection. The resulting design is fabricated using 40 nm bulk CMOS technology, and the proposed RX satisfies 3GPP requirements for reference sensitivity, in-band blocking, close-in blocking, and out-of-band blocking, making it a strong candidate for 5G local area base station applications.

Chapter 5 provides a brief discussion of the proposed ideas presented in this thesis and offers suggestions for future research directions.

The advent of fifth-generation (5G) wireless networks and their successors is poised to significantly enhance global economic productivity and societal connectivity. Central to this advancement is the power amplifier (PA), a critical component in radio frequency (RF) front-ends, which must efficiently amplify wideband OFDM signals with high peak-to-average power ratios (PAPR) under varying load conditions. Traditional PA designs rely on isolators to mitigate load sensitivity, but these are unsuitable for compact or high-frequency applications due to integration and cost constraints. This dissertation addresses the challenge of PA load resilience by introducing circuit topologies and adaptive techniques that eliminate the need for isolators. Key innovations include passive orthogonal impedance sensing, self-healing PA designs, and load-insensitive Doherty and inverse Doherty amplifiers. A standout contribution is a PA correction method using only active devices—without tunable networks or supply adjustments—ideal for high-power or fast-changing environments. These solutions are validated through PCB demonstrators, offering a path toward more efficient and resilient RF front-ends for future wireless systems.

The availability of millimeter-wave (mm-wave) communication systems is a key enabler in developing the fifth generation (5G) mobile networks that offer higher data throughput, lower network latency, and improved link robustness. Namely, they take advantage of mm-wave phased arrays to empower 5G communication systems that establish directional links with large bandwidths between the base station and user equipment. Despite this huge potential, mm-wave 5G has several natural disadvantages. The shorter wavelength of mm-wave signals results in lower penetrability, higher free-space path loss, and susceptibility to atmospheric attenuation, limiting network coverage. Additionally, 5G systems, offering high data throughput, require the use of complex modulation signals and, as such, need to handle large amplitude variations, complicating achieving high energy efficiency. Furthermore, their increased receiver noise lowers the sensitivity and link budget, while their use of Nanometer CMOS technology limits their transmit power and efficiency, impacting system reliability and thermalmanagement.
Unlike digital processors, whose performance and efficiency improve with semiconductor technology scaling, the performance of analog/RF front ends mainly relies on circuit and systemarchitecture innovations. Luckily, operating at mm-wave frequencies unlocks new opportunities, and an approach using those can exceed initial expectations. In this context, this dissertation introduces a series of innovative designs and techniques enhancing the performance and efficiency of power amplifiers (PAs) and transceivers for 5G mm-wave systems....

As 5G is rapidly growing, wireless communication systems require wideband, compact and highly efficient power amplifier modules (PA) to drive the base station antenna arrays. Doherty PAs are implemented in most base stations. The final stage in these power amplifier modules has high supply voltages (28-50 V) to generate a high output power of >20 W at reasonable output impedance levels. This work replaces the ‘classical’ single-ended cascode PA to drive the Doherty PA, with a series push-pull (or totem-pole) PA to increase the efficiency and bandwidth of the driver. The series push pull designs can reach peak efficiencies of 70.7%, which is about 10 percentage points higher than the efficiency of the single-ended PA. To ensure that a fair comparison is made between the designs, the series push-pull designs operate at 5 V and 10 V supply, in order to generate an output voltage swing of 5 V and 10 V respectively. This is compared to the single-ended PA with a 5 V supply and 10 V output swing. Simulation results show that the series push-pull design does indeed increase the efficiency of the driver whilst having minimal AM-AM distortion (<1 dB) at the design frequency of 3.6 GHz.

This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency.
To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency.

The demand for faster mobile access and higher data throughput drives the evolution of wireless cellular communication, requiring larger modulation bandwidths and higher-order modulations and necessitating more efficient and flexible transmitter systems.
Simultaneously, the advancements in nano-scale CMOS technologies have made transistors smaller and better suited for digital signal processing, with improved high-frequency performance for RF mixed-signal circuits.
These advancements impact wireless RF transceivers creating the need to explore transmitter architectures beyond the level of the most established ones, which are exclusively analog up to date, by pushing them towards incorporating more digital circuitry. Consequently, the primary research question addressed in this is: “What are the potential performance advantages when the strength of (high-speed) digital CMOS is utilized within an RF front-end?”
To answer this research question, this thesis proposes new architectures for digitalintensive transmitter line-ups. These architectures aim to enhance linearity, bandwidth, and power efficiency, and enable the full utilization of CMOS technology in digital operations within the RF front-end....

Wireless data traffic is projected to steadily increase in the near future, necessitating the demand for transceivers with higher linearity and efficiency. Digital power amplifiers have the potential to achieve these higher efficiency demands while digital pre-distortion can be used to improve their linearity. Digital pre-distortion requires a highly-linear wideband observation receiver to down-convert and monitor the output of the transmitter. An observation receiver architecture that relies on baseband error-detection has been previously proposed by ELCA to reduce the stringent requirements on the analog-to-digital converter (ADC) in such an observation receiver. This thesis work presents a novel extremely-linear wideband voltage-domain harmonic-reject mixer targeting these observation receiver applications. The choice for a voltage-domain mixer instead of a current-domain mixer is first discussed. Three novel voltage-domain mixer topologies are then evaluated for their advantages and disadvantages, yielding the preferred topology for implementation. This circuit was designed in TSMC40nm thin-oxide CMOS technology yielding promising performance metrics when compared to similar state-of-the-art publications in the open literature; specifically in domain of observation receiver applications.

N-path filters promise to miniaturize RF receivers by replacing various fixed off-chip filters with a single programmable on-chip filter. This research investigates some of the issues of receivers with N-path filters under strong blocker conditions: reciprocal mixing and inherent nonlinearity. First, a technique for reciprocal mixing cancellation is explored and shown to be impossible using only mixers and baseband impedances. Second, the inherent nonlinearity of both bandpass and notch N-path filters are simulated and modelled. To validate this approach, a highly linear receiver is proposed and designed in 40nm CMOS. The receiver has a bandpass common gate architecture, with a notch filter in the feedback path, improving linearity. The filter is isolated using buffers, improving LO leakage. The common gate stage is IM3 compensated to obtain good
linearity (OOB IIP3 >20 dBm).

This work presents a highly linear quadrature down-converter topology intended for the linearization of digital Transmitters(DTX). By integrating it with a DTX, a fully integrated on-chip output-signal correction loop comes closer to its realization. The proposed down conversion architecture can measure the errors introduced by the non-linearity of the transmitter, rather than the transmitter output itself. These errors are determined by comparing the downconverted transmitter output signals with its analog ideal baseband I and Q reference signals. The reference signals are provided by low-power digital-to-analog converters(DACs), using the same IQ data input as the power DTX. This approach reduces the resolution/dynamic range requirements on the trans-impedance-amplifier (TIA) and analog-to-digital converters(ADCs) since the error signals have a reduced dynamic range compared to the transmitter’s output signal itself. These lower requirements on the ADCs and elimination of off-chip couplers and filter sease the integration of a complete digital pre-distortion (DPD) correction loop in future DTX implementations. As the core of this thesis work, a linear harmonic rejection mixer was designed. It uses resistors inits mixer branches to implement the proper currenct scaling needed for harmonic rejection (HR). The resulting HR mixer avoids the unwanted down-conversion of the higher harmonics of the DTX to the base band frequencies of interest. Also, atrans-impedance amplifier was designed with the proposed passive mixer. These TIAs are based on an inverter topology for maximum tranconductance and were biased for optimal linearity and offered a bandwidth over 1.8GHz. The proposed DTX error-detection architectureis implemented in the current domain. Performing the subtraction before the TIA drastically reduces the voltage swing at the input of the TIA, benefiting the linearity of the mixer and reference DAC. The overall HR-mixer configuration is simulated for its linearity, yielding an IIP3 of 49dBm, which to the best of the author’s knowledge, is the best-reported linearity for high bandwidth down-converting applications.

Many applications require wide bandwidth transmitters, but unfortunately, they usually have way less than 50% average drain efficiency for their modulated signals. This low efficiency is a significant drawback in all wireless applications, both for battery power devices and base stations. The Doherty radio frequency (RF) power amplifier architecture is widely used to enhance the average efficiency for modulated signals in base stations. Its popularity is due to its relatively cheap and simple hardware and its suitability to handle high-power wideband modulated signals. However, even Doherty amplifiers often have less than 50% average efficiency and are restricted in their RF bandwidth.
This thesis reviews recent research on the Doherty power amplifier (DPA) topology and discusses possible power and bandwidth efficiency improvements. In the second part of the thesis, another topology is introduced, which also provides Doherty-like behavior. That topology is called a Pseudo Doherty Load Modulated Balanced Amplifier (PD-LMBA). The performance of PD-LMBA is compared with “conventional” DPAs. Circuit design examples of DPA and PD-LMBA are given. The thesis concludes with a PD-LMBA prototype design, which appears to be very promising in its wideband performance.

This thesis investigates the performance limits and design challenges of two current-mode front-end concepts that target WiFi and mm-wave 5G applications, respectively. The first concept is a power amplifier (PA), which operates at 2.4GHz and is driven by a direct-digital RF modulator (DDRM). A design for the PA, which also includes a parallel-combining transformer (PCT), was proposed, taped and tested in the QUBiC Gen8 technology of NXP Semiconductors. The measured results yield a peak output power of 27dBm, power efficiency of 20%, and an adjacent channel power ratio (ACPR) of -33.05dBc. In the other concept, the DDRM drives a power mixer (PMIX) which up-converts the DDRM signal to mm-wave frequencies. For the PMIX-based front-end, multiple linearity enhancement techniques were proposed and evaluated using simulations. For both current-mode front-end concepts, an extensive analysis on the theoretical output power and power efficiency limit was performed. Although current-mode operation has a high linearity potential, fully reaching this potential turns out not to be trivial, due to various device non-idealities and imperfect impedance matching.

This thesis focuses on digital-intensive up-converters for sub-6GHz wireless communication. Nowadays, wireless cellular communication is entering its 5th generation (5G), driven by the demand for faster mobile access and higher data throughput. 5G utilizes larger modulation bandwidths, higher-order modulations, and (many) more transmitters and receivers than its precessors, requiring higher system efficiency, flexibility, and integration of the transmitter (TX). An essential building block in the TX system is the RF modulator that converts the baseband data to an RF signal. New modulator architectures and circuits are required to handle the increased 5G modulation bandwidths linearly and energy-efficiently. Along with the progress in wireless communication, nano-scale CMOS technologies are advancing toward their physical limitations. Transistors have become smaller and more suited towards digital signal processing (DSP). Moreover, their high-frequency performance has improved, enabling RF analog/mixed-signal circuits. These improvements offer digital-intensive transmitters (DTXs) the opportunity to enter a territory that has been the traditional stronghold of analog-intensive TXs. Consequently, the research question of this dissertation is “What if we change the nature of the RF front-end, such that we can start truly benefiting from the power of CMOS in “digital” (switching) operations?” This thesis proposes new digital-intensive TX line-ups and up-converters architectures with enhanced linearity, bandwidth, and power efficiency to answer this question...

CMOS technology is one of the feasible solutions to meet the world’s growing demand for high data rates because it offers the prospect of SoC at a low cost. But, the PA forms the major bottleneck in making SoC because the PAs in high data rate wireless communication systems have the requirement of high-efficiency and good linearity even at backed-off power levels. Currently, PAs are mostly of classes A and B. Both of these are linear, but peak efficiencies are only 50% and 78% respectively. This thesis focuses on implementing Continuous Class F (CCF) PA for WiFi 802.11n over the bandwidth 2.1 - 2.7 GHz, which meets the requirement of high efficiency and good linearity even at backed-off power levels. The CCF PA overcomes Class F’s disadvantage of limited bandwidth as well as maintains peak efficiency of 90.7% over the entire bandwidth. The designed PA has four main blocks: the driver, inter-stage matching, output network, and output stage. The procedure to implement each of these blocks is explained extensively in chapters 3, 4, 5, and 6. The layout of the chip is carried out in TSMC 40 nm, and the chip size is 1.4 mm2. From simulations, the CCF PA has a maximum efficiency of 30 % and EVM of -25 dB at 3 dB back-off across the bandwidth 2.1 -2.7 GHz. The tapeout of the chip is planned in March 2021. Later, the chip can be tested and simulation results will be validated. To the best knowledge of the author, this is the first CCF chip at 2.4 GHz band.

This thesis presents the development of circuits and systems for fast wireline transceiver links that will enable a move towards highly integrable RF digital-to-analog converters. A new perspective on the analysis of bit error rates in wireline links leads to the PAM spectral design space chart: a novel, visual system design analysis tool for PAM wireline circuit designers. Moreover, a <2 mW/Gbps/lane, 10 Gbps wireline transmitter has been designed and taped-out in 40 nm CMOS. The proposed inherently pipelined 16:1 multiplexer and current mode logic driver design procedure are the key enablers for this performance. Finally, for development of a 10 Gbps wireline receiver, a novel self-synchronized receiver design is proposed that removes the need of a classical clock and data recovery loop. At its core, this receiver comprises the design of a high-speed two-tail comparator and an asynchronous metastability detection loop.

The ever increasing demand for faster data rates combined with the need for higher levels of integration, while keeping the production and operation cost to a minimum leads to the requirement of an efficient high bandwidth digital transmitter architecture. With the shortcomings of both polar and cartesian architectures, a new architecture is introduced.

In 5G transmitters, high efficiency, high linearity, and compatibility with MIMO and beamforming techniques are of utmost importance. Typically, enhancement techniques like supply modulation or load modulation are used when dealing with envelope modulated communication signals, which increasingly have high peak-to-average-power ratios (PAPR). Supply modulation is most favored in handsets. Techniques like "Envelope Tracking (ET)" or "Envelope Elimination and Restoration (EER)" are employed to generate high efficiency over a large power back-off range. These techniques are robust to antenna impedance variations compared to load modulation techniques like Doherty. However, the downside of supply voltage modulation is the need for a dynamic supply modulator. Such supply modulators are very difficult to implement for systems with video bandwidths >20MHz. For modern communication systems like 5G, video bandwidths for both the base stations and handsets are drastically increasing (up to ~1GHz). 5G communication is also going to operate at very high frequencies, commonly known as mm-wave. This degrades the efficiency of the transmitter because of increased losses in the output conductance of the active device and from any power combining network. Furthermore, due to the use of (massive) MIMO/smart-antenna techniques in these 5G base stations, there will also be undesired time-fluctuating antenna impedances due to PA back-coupling through the antenna array, which are extremely difficult to handle in efficiency enhancement techniques based on load modulation. In this thesis, a new type of wideband "supply voltage modulation" has been investigated. The aimed concept uses multiple constant supply voltages rather than a single time variant dynamic voltage supply. Several "parallel" PA devices are connected to different DC supply voltages while their RF output terminals are AC connected. The PA connected to a lower DC supply is used in the low power region, while the PA with a higher DC supply is used in the high power region. This ensures that the DC power consumption is output power dependent. By gradually controlling the amplifier branches through their RF inputs, proper transitions can be made between the different amplifier branches (i.e., from low power to high power region and vice versa)

Recent years have seen an exponential growth in required wireless data capacity. This exponential growth is expected to continue, while it is unsustainable if the power consumption associated with it will grow at the same rate. This calls for better power efficiency, which can usually be found in polar power amplifier architectures. This thesis focuses on the feasibility of a power RF-DAC, with as main focus to seek improvement in power efficiency. As all information up to the RF output is in the digital domain the design will be frequency agile, meaning that operation frequency is only dependent on the external matching network.
As starting point an existing LDMOS technology is considered to implement a power Digital-to-RF-Amplitude Converter (DRAC) with a dedicated CMOS driver. As first demonstrator these two chips could be connected using flip-chip bonding. The proposed combination allows a maximum operation frequency of 3 GHz, providing a peak fundamental output power of 16,6 W with a drain efficiency of 64,4 % at the maximum operation frequency. Since the CMOS driver operates in Class-D a significantly lower average driver power consumption is expected compared to an analog system where a Class-A or Class-AB predriver would be used. This promising concept can change the way how future transmitters could be constructed. In conclusion a performance outlook will be given if a dedicated high power silicon technology that can feature the CMOS drivers would be available for 4G/5G applications.