Voltage regulator for CMOS Drivers in RF-DACs

Abstract

This thesis presents the design of a bidirectional low-dropout voltage regulator(LDO) for CMOS drivers in a 3.5 GHz digital transmitter (DTX). A tightly regulated 0.9V mid-rail supply is required to ensure short rise/fall times and maintain Adjacent channel leakage ratio(ACLR) performance. Regulator specifications were derived by porting the LDMOS driver to a 22 nm FDSOI process and characterizing its current demand across PVT corners, requiring up to 2.9 mA sourcing and 1.9 mA sinking with < ±1.5 mV voltage deviation. A complementary push–pull architecture with a folded-cascode error amplifier, super-source-follower buffers, and differentiator-based compensation was implemented to achieve low output impedance without excessive on-chip capacitance. Simulations confirm < 573 μA quiescent current, phase margin > 45°, and acceptable ACLR performance, validating the design for integration in CMOS/LDMOS DTX systems.