Mobile data demand and capacity have grown exponentially for decades. This trend is expected to continue in the coming years, and new techniques and communication standards are being adopted to accommodate this growing demand. The energy consumption of the mobile networks associated with this growth is of specific concern, with an estimated 3.6 % of the global electrical energy being consumed by 2030. The exponentially growing data capacity is enabled by the tremendous technological development in integrated circuits (ICs), specifically in the domain of digital-oriented CMOS technologies. With digital logic becoming ever faster, their switching performance provides new opportunities for RF transmitters. Over the last decade, this has led to enormous progress in digital transmitters (DTXs).

However, the typical supply voltages of digital-oriented CMOS technologies are too low to reach the power levels required for mMIMO base stations. The market for high-power RF applications optimizes their technologies for minimized losses, and increased power density and gain. This results in a performance gap between what digital CMOS can provide today and what is required for next-generation base stations. Benefiting from the increased functionality and power savings from the developments in digital CMOS while maintaining the power levels provided by technologies—such as LDMOS or GaN—is taking the best of both worlds. This leads to the research objective of this dissertation:
"How can digital-oriented low-power CMOS technology be combined with high-power RF technology such that energy-efficient operation of next-generation sub-7 GHz base stations can be achieved?"
To answer this question, several demonstrators have been designed to pioneer combining CMOS technologies with high-power RF technologies.

The knowledge gained from designing these demonstrators is presented in the early chapters of this dissertation, providing the reader with important aspects of designing high-power DTXs. This ranges from practical aspects of the heterogeneous integration used, such as electrical compatibility and packaging, to designing high-speed drivers and the high-level modeling of DTXs. A mathematical definition of a DTX's transfer is proposed, which relates its numerical baseband input to the output power at RF. Further, a power model capable of estimating DTX performance in terms of power and efficiency is proposed. This power model combines the theory, presented in the chapters before, into a handful of equations that describe the power relations in a DTX by first-order approximation, which are useful for hand calculations and can help conceptual understanding of the underlying relations. These background chapters guide the reader in implementing future high-power DTXs, and the power relations can be used to optimize these future designs from both the digital CMOS and power technology perspectives.

The RF performance of current-scaling digital transmitters (DTX) with polar, unsigned Cartesian, signed Cartesian, and multiphase architectures have been compared regarding power utilization of their output-stage switch banks and drain efficiency. The analysis includes various switch bank operation modes, such as switch bank sharing, segment activation interleaving, and their activation times (RF duty cycle of the segments). Current-scaling DTXs can be made compatible with high-power operations while offering high system efficiency and RF bandwidth. The average efficiency using Doherty power back-off efficiency enhancement is analyzed, and a comparison of the different proposed DTX implementations is presented.

An implementation strategy for high-power, high resolution, fully digital transmitters (DTX) is proposed. It is based on a high-speed CMOS controller featuring a high-density flip-chip interconnect to an LDMOS power MMIC containing large arrays of custom low-VT LDMOS gate segments configured in RF-power switch banks. Using a two-level thermometer approach and a novel symmetric control scheme for the activation of the gate segments, a high-resolution 11-bit DTX switch bank is realized. It can provide peak RF powers >10 W at 45/40% peak drain/system efficiency at 3.525 GHz.

A current-mode direct-digital RF modulator (DDRM)-based transmitter (TX) architecture is proposed in this article for energy-efficient wireless applications. To demonstrate its key principles, a 2×13 bit demonstrator is implemented in a 40-nm CMOS technology. This DDRM can operate standalone or as a driver for a common-gate (CG)/common-base (CB) power amplifier (PA). The proposed DDRM is based on current-steering radio frequency digital-to-analog converters (RFDACs) that feature an extra current division path to allow the generation of the optimum current-mode class-B drive profile for the final CG/CB PA, facilitating energy-efficient TX operation without compromising linearity. For this purpose, the DDRM uses signed-IQ mapping combined with a class-B harmonic rejection (HR) technique. In addition, an advanced dynamic biasing technique is introduced to further enhance the TX line-up efficiency in deep power back-off (PBO) region. The DDRM driver standalone can provide 19.6-dBm RF peak output power. It supports a '160-MHz 256-QAM' signal at 2.4 GHz with an adjacent channel leakage ratio (ACLR) of -40.3 dBc and an error vector magnitude (EVM) of -33 dB, without using any digital pre-distortion (DPD). When connected to a CB SiGe PA, the overall TX line-up achieves an output power of 27 dBm and an overall TX system efficiency of 20%. This DPD-free TX line-up achieves an ACLR of -37.7 dBc and an EVM of -30 dB, respectively, when operating with an '80-MHz 64-QAM' signal at 2.2 GHz.

Fully digital transmitters (DTXs) have the potential of replacing analog-intensive transmitter (TX) line-ups in future massive multiple-input and multiple-output (mMIMO) systems since they hold the promise of higher system integration level and energy efficiency. DTX operation so far has been limited to low RF output powers. This article introduces a concept that enables high-power DTX operation. A DTX demonstrator targeting both high output power and high efficiency is realized as a proof of concept. It is based on a custom <formula> <tex>${V_{T}}$</tex> </formula> -shifted laterally-diffused MOS (LDMOS) technology, which is utilized to implement a segmented high-power output stage operated in class-BE. A low-voltage high-speed 40-nm CMOS controller drives the individual output stage segments at gigahertz rates. Measurements show the promising results for the proposed high-power DTX concept and provide valuable lessons for future DTX implementations.

A high-power fully-digital Doherty transmitter (DDTX) is proposed. It features two segmented LDMOS output switch banks implemented in a custom V T -down-shifted LDMOS technology. A 40 nm CMOS controller digitally activates the individual LDMOS gate segments of the output stage at RF speed. An inverted Doherty power combiner is proposed that features non-short circuited 2 nd harmonic conditions for the main and peak switch banks to boost the RF bandwidth. To guarantee smooth output power and efficiency vs. frequency, a 2 nd harmonic trap is introduced in the power combiner, yielding an RF bandwidth of > 400 MHz. The realized demonstrator can achieve over 39 W peak output power. Its highest drain and system efficiencies, respectively 60 % and 57 %, were found at 34.2 W of output power, while in power back-off its peak drain and system efficiencies are 52 % and 48 % respectively. Over a 25 dB output range, the system efficiency is within 4 percent points of the drain efficiency.

This article presents a wideband 2× 12 -bit direct-digital RF modulator (DDRM) operating in a 0.5-to-3-GHz band for 5G transmitters. The proposed digital Cartesian modulator features an advanced IQ-mapping technique to boost RF power by 3 dB and suppress the I/Q image. To verify the proposed concept, a 40-nm CMOS prototype is implemented whose RF peak output power at 2 GHz is more than 14 dBm. It achieves an adjacent-channel leakage ratio (ACLR) of -52 dBc and an error vector magnitude (EVM) of -40 dB for a 20-MHz 256-QAM signal at 2.4 GHz. With a 320-MHz 256-QAM signal, the measured ACLR and EVM performances are better than -43 dBc and -32 dB at 2.4 GHz, respectively, without using any digital pre-distortion.

An energy-efficient, intrinsically linear, digital class-C like operation-mode is investigated for use in high-power digital transmitters (DTXs), which target next generation mMIMO base stations that offer lower costs, higher integration, and improved system efficiency. The proposed operation utilizes class-B/C output matching in combination with duty-cycle reduction and current-mode operation of a segmented output stage. Its performance in terms of efficiency, output power, and linearity is benchmarked with analog class-B/C operation. The proposed digital class-C like operation has been experimentally verified using a fully-digital, dual TX line-up with VT-shifted segmented LDMOS output stages. All output stage segments are individually controlled by high-speed digital drivers implemented in 40 nm CMOS technology. The realized prototype provides 25.9 W (CW) output power with 75.7 % drain and 72.9 % system efficiencies, at 930 MHz and at 28 V drain supply.

A high-power digital transmitter (DTX) concept, targeting future low-cost, highly-integrated and energy-efficient mMIMO base stations, is presented. The proposed approach bridges the 'historical' gap between low-voltage high-speed digital and high-voltage high-power RF devices. The resulting combination allows for a complete replacement of the traditional TX line-up, which includes signal-generation, up-conversion, and analog pre-drivers and power amplifier (PA), as such, facilitating drastic energy savings. The DTX principles are demonstrated by a dual TX line-up implemented in a dedicated VT-shifted LDMOS technology. Each 11-bit DTX line-up features 15 thermometer and 7 binary-weighted LDMOS output-stage segments, which are individually controlled by digital logic and high-speed drivers implemented in 40 nm CMOS technology. The realized DTX prototype exploits a 2.1 GHz centered class-BE output matching network and provides, at 20 V drain supply, 18.5 W (CW) output power with 66.7 % drain and 60.4 % system efficiencies. The suitability of the concept to handle modulated signals is demonstrated for a two-tone signal (Δf = 80 kHz), yielding an 1M3 < -51.4dBc and a 10MHz 256-QAM signal, achieving an ACLR of -46.1 dBc and 1.2 % EVM.

This paper presents a wideband, 2× 12 -bit I/Q interleaved direct-digital RF modulator (DDRM) realized in 40 nm CMOS technology. The proposed digital-intensive quadrature upconverter features an advanced I/Q-mapping unit cell to boost RF power, in-band linearity, and out-of-band spectral purity. The modulator provides more than 14 dBm RF peak output power. It achieves an ACLR of -52 dBc and an EVM of -40 dB when applying a 20 MHz 256 QAM signal at 2.4 GHz. When applying a 320 MHz 256 QAM signal at 2.4 GHz, the measured ACLR and EVM are better than -43 dBc and -32 dB, respectively, without applying any digital pre-distortion.

We present a 1-3 GHz, 2×13-bit I/Q interleaved direct-digital RF modulator (DDRM) realized in 40 nm CMOS technology as a driver for an external common-gate (CG) power amplifier (PA). The proposed digital-intensive quadrature up-converter features a pair of novel current-steering mixing DACs with an additional leakage path to boost the efficiency of the external CG PA. The realized DDRM also employs IQ-interleaving, harmonic rejection, and dynamic biasing to improve its spectral purity, in-band linearity, and system efficiency. The proposed digital up-converter prototype provides standalone more than 19.6 dBm RF peak output power. Without using any digital pre-distortion, it achieves an ACLR of-44.5 dBc and an EVM of-35 dB, when applying an 80 MHz 256 QAM signal at 2.4 GHz.