M.J. Pelk
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4 records found
1
The developed hardware employs a cascade of two (COTS) programmable gain amplifier (PGA), capable of reaching up to 90 dB gain (volt to volt), each providing an input referred noise level of 16 nV/√Hz. The signal is then digitized on the same board via a 500 kHz 12bit ADC, providing an SNR of 74 dB. The digitized signal is then readout via an ST microcontroller and transferred to the operator PC via a USB interface. The sensitive bias voltages for the PGAs are provided via the microcontroller, or alternatively can be fed by an external lab grade supply to further improve on the (already high) supply noise rejection from the first stage PGA. The proposed hardware is designed to interface with VDI zero bias detectors, high responsivity and low NEP diodes (around 2000 V/W and below 12 pW/√Hz, respectively) operating in monomodal waveguide bands up to 500 GHz. In this contribution we demonstrate the usage of the developed hardware with WR10, WR6.5, WR5 and WR 3 ZBD diodes. ...
The developed hardware employs a cascade of two (COTS) programmable gain amplifier (PGA), capable of reaching up to 90 dB gain (volt to volt), each providing an input referred noise level of 16 nV/√Hz. The signal is then digitized on the same board via a 500 kHz 12bit ADC, providing an SNR of 74 dB. The digitized signal is then readout via an ST microcontroller and transferred to the operator PC via a USB interface. The sensitive bias voltages for the PGAs are provided via the microcontroller, or alternatively can be fed by an external lab grade supply to further improve on the (already high) supply noise rejection from the first stage PGA. The proposed hardware is designed to interface with VDI zero bias detectors, high responsivity and low NEP diodes (around 2000 V/W and below 12 pW/√Hz, respectively) operating in monomodal waveguide bands up to 500 GHz. In this contribution we demonstrate the usage of the developed hardware with WR10, WR6.5, WR5 and WR 3 ZBD diodes.
An energy-efficient, intrinsically linear, digital class-C like operation-mode is investigated for use in high-power digital transmitters (DTXs), which target next generation mMIMO base stations that offer lower costs, higher integration, and improved system efficiency. The proposed operation utilizes class-B/C output matching in combination with duty-cycle reduction and current-mode operation of a segmented output stage. Its performance in terms of efficiency, output power, and linearity is benchmarked with analog class-B/C operation. The proposed digital class-C like operation has been experimentally verified using a fully-digital, dual TX line-up with VT-shifted segmented LDMOS output stages. All output stage segments are individually controlled by high-speed digital drivers implemented in 40 nm CMOS technology. The realized prototype provides 25.9 W (CW) output power with 75.7 % drain and 72.9 % system efficiencies, at 930 MHz and at 28 V drain supply.
A low-cost, highly versatile, pulsed RF - pulsed I-V isothermal device characterization setup is presented. The realized setup combines a synthetic instrument high dynamic range pulsed network analyzer with pulsed I-V measurements. The resulting configuration facilitates very accurate characterization of low-power as well as high-power devices over a wide range of bias and pulse conditions. The achieved system accuracy is reported, and its measurement capabilities are highlighted through the characterization of self-heating effects in LDMOS devices and silicon-on-glass VDMOS.