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E. Shokrolahzade

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9 records found

Journal article (2026) - G. Simoncini, E. Shokrolahzade, G. Schiavolini, G. Orecchini, G. Fischer, C. Carta, M. Spirito, F. Alimenti
Avalanche driven diodes have been traditionally used as electrical noise generator due to their capability of generating broadband random noise. Currently, no solutions have been reported to generate avalanche noise at cryogenic temperatures. This work represents a step toward addressing this gap. For the first time, we present the full characterization of two millimeter-wave noise sources (NSs) operating at cryogenic temperatures: the first based on the base-collector diode of an heterojunction bipolar transistor (HBT) driven into avalanche, while the second based on a p-i-n diode integrating the bias circuitry and the output attenuator. Both devices, fabricated using two different 130-nm silicon-germanium (SiGe) BiCMOS process and assessed as NSs at room temperature (RT), have now been demonstrated to operate reliably and efficiently for physical temperatures as low as 4.3 K. Both devices are measured over a complete cooling cycle with mid temperature points (i.e., 300, 70, 4.3) during cooling and warming cycle, to assess that no hysteresis or memory effect are present in their behavior. The reported excess noise ratio (ENR) of the HBT-based diode shows a maximum variation of about 1 and 0.5 dB for 2 and 4 mA bias currents, respectively, in the range of 1–40 GHz. For the same biasing ranges, the p-i-n NS showed a maximum variation of 2 dB at 30 GHz (on-chip attenuator included) resulting in a temperature sensitivity of about −0.007 dB/K. The reported results highlights the capability of such devices to realize a new class of integrated high performance cryogenic sources, opening the possibility to integrated in situ cryogenic calibrations. ...
This paper presents a mm-wave non-magnetic balanced circulator that bridges the gap between the high insertion loss (IL) of electrical balance duplexers and the transmitter (TX)to-receiver (RX) isolation degradation of conventional circulators under varying antenna (ANT) voltage standing wave ratio (VSWR). Using quadrature couplers, a balance network, and (non)-reciprocal branches, it achieves <5.2dB TX-to-ANT IL, <4.2dB RX-to-ANT IL, and >20dB TX-to-RX isolation over a >2.2GHz bandwidth at VSWR=2. ...
Journal article (2025) - E. Shokrolahzade, F. A. Mubarak, J. Wiedmayer, C. De Martino, L. Oberto, F. Sebastiano, M. Spirito
Increasing demand for cryogenic electronics aimed at quantum sensors and computing technologies asks for accurate and quantifiable calibration methods and techniques. In this work, we present a structured approach to generate the nominal RF responses of standard artifacts, enabling wideband vector network analyzer (VNA) calibration algorithms, i.e., short, open, load, and reciprocal (SOLR), at cryogenic temperatures. Moreover, we present an EM simulation strategy to generate the perturbations in the artifacts’ responses based on mechanical fabrication tolerances and calculate an equivalent RF response uncertainty. Both the nominal and perturbed standard responses are computed at (user defined) cryogenic temperatures, by combining thermo-mechanical responses with the electromagnetic solver. A circuit simulator-based measurement model (MM) is used to compute the uncertainties of the cryogenic setups used in this work. Error contributions arising from the propagation of VNA noise, switch nonidealities, calibration artifacts uncertainties, temperature fluctuations, and temperature gradient over the interconnects are included in the MM. For validation, measured results of a coaxial air transmission line at 77 K and 4.2 K are presented and compared with 3-D EM simulation predictions. Finally, the measurement uncertainties are detailed in a budget analysis describing the individual contributions. ...
Journal article (2025) - Carmine De Martino, Ciro Esposito, Eduard Satoshi Malotaux, Steffen Lehmann, Zhixing Zhao, Sven Mothes, Claudia Kretzschmar, Ehsan Shokrolahzade, Michael Schröter, Marco Spirito
This work presents a structured, CAD-assisted design flow to realize broadband on-wafer calibration structures, validated in the prefabrication phase, and extract the intrinsic device response up to (sub)mm-waves. The strict requirements imposed by the design rule checks (DRCs) of 22 nm CMOS technology are incorporated during the design phase of the fixture by using a scripted connectable tile elements approach. The minimum dimension of a critical feature of the fixture is then identified using a newly defined metric based on the correspondence between the EM field distribution in the fixture versus a non-perturbed case of the same standard (STD) artifact. A simulation test bench environment, augmented with experimental data, is then used to add the uncertainties arising from three main error contributors: vector network analyzer (VNA) receiver noise, probe placement error, and calibration residual errors. Including these errors allows for the generation of pre-silicon numerical uncertainty bounds, which are benchmarked with experimental data using calibration quality metrics and device-level parameters. Measurement results ranging from 1 to 325 GHz are presented to demonstrate the validity of the proposed approach to establish the quality of on-wafer calibration approaches integrated in the back-end of line of Si-based technologies and to validate the compact model of CMOS devices up to (sub)mm-waves. ...
In this work, we present a numerical testbench, realized in a circuit simulation environment, enabling a priori uncertainty evaluation of dielectric spectroscopy in the application field of organs-on-chip. This testbench evaluates the impact of noise, ambient temperature variation and impurity of liquid standards on the uncertainty of dielectric spectroscopy measurements. Moreover, the proposed approach allows to account for the impact on measurement sensitivity of system parameters such as probe dimensions and probe coatings. The estimated uncertainty contributions for the considered effects are compared and benchmarked experimentally. Finally, the testbench is employed to project the dielectric spectroscopy accuracy on a relevant biological application, namely monitoring the growth of a 7 μm-thick kidney cell monolayer. ...
Conference paper (2024) - B. Louwes, M.J. Pelk, J. Bueno, E. Shokrolahzade, C. De Martino, M. Spirito
In this paper, we present a low-noise, high-gain readout hardware to be used in conjunction with (sub)mm-wave zero bias detectors, to enable high sensitivity (i.e., ∼-50dBm) and fast (i.e., below a second at -50 dBm) power detection.

The developed hardware employs a cascade of two (COTS) programmable gain amplifier (PGA), capable of reaching up to 90 dB gain (volt to volt), each providing an input referred noise level of 16 nV/√Hz. The signal is then digitized on the same board via a 500 kHz 12bit ADC, providing an SNR of 74 dB. The digitized signal is then readout via an ST microcontroller and transferred to the operator PC via a USB interface. The sensitive bias voltages for the PGAs are provided via the microcontroller, or alternatively can be fed by an external lab grade supply to further improve on the (already high) supply noise rejection from the first stage PGA. The proposed hardware is designed to interface with VDI zero bias detectors, high responsivity and low NEP diodes (around 2000 V/W and below 12 pW/√Hz, respectively) operating in monomodal waveguide bands up to 500 GHz. In this contribution we demonstrate the usage of the developed hardware with WR10, WR6.5, WR5 and WR 3 ZBD diodes. ...
Conference paper (2024) - Aniello Franzese, Batuhan Sutbas, Corrado Carta, Thomas Mausolf, Nicolò Moroni, Renato Negra, Alfredo Sánchez Ramos, Francesco Greco, Luigi Boccia, Ehsan Shokrolahzade, Marco Spirito
This work describes accurate methods for the characterization of sub-terahertz (sub-THz) devices and pad de-embedding procedures. The extraction of the intrinsic DUT is enabled by generating a precise pad model using two-tier calibration approaches. Moreover, the proposed approaches offer a solution to the designers to preserve precious silicon area by presenting a simplified and potentially parameterizable pad model. Employing two different thru-reflect-line (TRL) calibration kits (calKits) together with the DUT on the same die, this research validates the proposed calibration strategies. This paper uses as DUT at J-band, i.e. a Marchand balun, fabricated using IHP SiGe BiCMOS technology with an aluminum back-end-of-line (BEOL), alongside the mentioned calKits. The goal of the paper is to assess the performance of the DUT and validate two de-embedding methods. Moreover, the pad model offers a way for accurate DUT characterization saving silicon area for future optimized designs. ...
In this contribution, we describe the modeling approaches and the characterization procedures used to develop accurate standard models for cryogenic, probe-level, calibrations substrates.The key electrical and mechanical parameters of the impedance terminations and the lines used in commercially available impedance standard substrates are first characterized versus temperature. After, these component are simulated using 2.5D EM solvers including their mechanical variation when exposed to cryogenic temperatures, to extract their nominal response at 7 Kelvin. The quality of the resulting calibrations at cryogenic is evaluated first using independent CPW lines on the calibration substrates and then by measuring the response of a transformer-based resonator realized on a Si-based technology.Ambient temperature models are used as a comparison, to highlight the accuracy improvement that can be achieved employing optimized Cryo-EM based models. ...
Conference paper (2023) - Ehsan Shokrolahzade, Carmine De Martino, Marco Spirito
In this contribution we present an approach to reduce the error arising from the variations of the lumped load, due to process spread, in probe level calibrations. First, full-wave electromagnetic (EM) simulations are employed to generate the nominal standard responses, then a parametric EM simulation of the load structure is used to generate a parametrized model of the standard. The approach is tested using a Short-Open-Load-Reciprocal calibration algorithm and an impedance standard calibration substrates developed on a 150 mm Quartz wafer (400 pm thick). In this process the high fidelity of the lateral dimension of the fabricated structures, realized using IC Photolithography, allows to confine the variations of the load response to only the thin-film resistor thickness spread. The DC response of the load, measured during the calibration step, is used to identify the specific RF response of the probed load from the parametric model. A complete analysis using full-wave EM simulations accounting for process variation is presented together with a set of experimental data up to 67GHz. ...