This work presents a chessboard focal plane array (FPA) camera with state-of-the-art thermal and spatial resolution in the 200 600 GHz frequency range. The FPA is implemented in a 130-nm SiGe BiCMOS technology, where each antenna element is loaded with a direct detector based on heterojunction bipolar transistors (HBTs). The antenna and detector architecture, including the vias and biasing network, were optimized to achieve a noise-equivalent power (NEP) suitable for passive THz imaging. Overall, the estimated loss of the FPA is better than 4 dB between 350 and 600 GHz, of which 1.5 dB is due to ohmic losses in the FPA, 1 dB to mutual coupling between detectors, and 0.7 dB to the impedance mismatch between the detector and antenna. A prototype of 24 pixels was manufactured and mounted on the base of a silicon hyperhemispherical lens with an anti-reflection coating. Excellent spatial resolution is achieved through a tight element spacing in the fabricated FPA, which is only half the wavelength in silicon at 350 GHz and therefore consistent with the state-of-the-art. Its responsivity, noise, and radiation patterns were characterized using a quasi-optical measurement setup. The measured radiation patterns are within 1 dB of simulations, demonstrating that the integrated THz camera achieves excellent spatial resolution. Between 330 GHz and 500 GHz, the NEP was measured to be on the order of 10 pW/vHz. When considering the entire operational band, this NEP results in a noise-equivalent temperature difference (NETD) of the camera is 1.6 K for an integration time of 1 s per pixel, which is comparable to the state-of-the-art. While THz detectors with state-of-the-art sensitivity are limited to single-pixel designs, the presented work combines a multi-pixel implementation with competitive sensitivity.

This work describes accurate methods for the characterization of sub-terahertz (sub-THz) devices and pad de-embedding procedures. The extraction of the intrinsic DUT is enabled by generating a precise pad model using two-tier calibration approaches. Moreover, the proposed approaches offer a solution to the designers to preserve precious silicon area by presenting a simplified and potentially parameterizable pad model. Employing two different thru-reflect-line (TRL) calibration kits (calKits) together with the DUT on the same die, this research validates the proposed calibration strategies. This paper uses as DUT at J-band, i.e. a Marchand balun, fabricated using IHP SiGe BiCMOS technology with an aluminum back-end-of-line (BEOL), alongside the mentioned calKits. The goal of the paper is to assess the performance of the DUT and validate two de-embedding methods. Moreover, the pad model offers a way for accurate DUT characterization saving silicon area for future optimized designs.