Jv
J.M.M. van der Meulen
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2 records found
1
Conference paper
(2017)
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M. D'Avino, J.M.M. van der Meulen, E.S. Malotaux, M Pelk, L.C.N. de Vreede, M.W.A Groenewegen, P. Mattheijssen, M.P. van der Heijden
A linearization technique for bipolar amplifiers based on Derivative
Superposition is presented. The proposed technique provides excellent
linearity, while having low sensitivity on the bias conditions. A
demonstrator circuit, along with a reference circuit using out-of-band
linearization for linearity comparison, have been designed and
implemented in a 0:25μm SiGe:C BiCMOS technology to show the
effectiveness of the proposed approach. Measured results show a
significant IM3 improvement up to compression compared to the reference
circuit.
...
A linearization technique for bipolar amplifiers based on Derivative
Superposition is presented. The proposed technique provides excellent
linearity, while having low sensitivity on the bias conditions. A
demonstrator circuit, along with a reference circuit using out-of-band
linearization for linearity comparison, have been designed and
implemented in a 0:25μm SiGe:C BiCMOS technology to show the
effectiveness of the proposed approach. Measured results show a
significant IM3 improvement up to compression compared to the reference
circuit.
A frequency, bias and output power independent linearization technique for reducing the non-linear base-collector capacitance related distortion is proposed. Based on Volterra series analysis, the optimum base-collector capacitance for linear device operation is determined while respecting physical constrains. It is shown that by modifying the extrinsic base-collector region for an otherwise uncompromised device, the Cbc linearity compensation can be included within the transistor design itself. The practicality of this implementation is demonstrated by considering the doping profile accuracy requirements for achieving a significant OIP3 improvement of at least 5dB.
...
A frequency, bias and output power independent linearization technique for reducing the non-linear base-collector capacitance related distortion is proposed. Based on Volterra series analysis, the optimum base-collector capacitance for linear device operation is determined while respecting physical constrains. It is shown that by modifying the extrinsic base-collector region for an otherwise uncompromised device, the Cbc linearity compensation can be included within the transistor design itself. The practicality of this implementation is demonstrated by considering the doping profile accuracy requirements for achieving a significant OIP3 improvement of at least 5dB.