Fully digital transmitters (DTXs) have the potential of replacing analog-intensive transmitter (TX) line-ups in future massive multiple-input and multiple-output (mMIMO) systems since they hold the promise of higher system integration level and energy efficiency. DTX operation so far has been limited to low RF output powers. This article introduces a concept that enables high-power DTX operation. A DTX demonstrator targeting both high output power and high efficiency is realized as a proof of concept. It is based on a custom <formula> <tex>${V_{T}}$</tex> </formula> -shifted laterally-diffused MOS (LDMOS) technology, which is utilized to implement a segmented high-power output stage operated in class-BE. A low-voltage high-speed 40-nm CMOS controller drives the individual output stage segments at gigahertz rates. Measurements show the promising results for the proposed high-power DTX concept and provide valuable lessons for future DTX implementations.

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Recently, digital transmitters (DTXs) that feature arrays of controlled digital PA (DPA) cells have become increasingly popular since they directly benefit from nanoscale CMOS technology, yielding reduced die area and highly efficient operation [1] -[6]. For wideband applications, I/Q DTXs are considered superior over their polar counterparts due to their linear I/Q operation, which avoids bandwidth expansion. Nevertheless, I/Q DTXs can suffer from the interaction between their I and Q paths, especially at higher power levels, giving rise to an I/Q image and nonlinearity. To tackle this issue, an IQ interleaved upconverter has been introduced [1]. However, its 25%-LO requirement restricts the operational frequency to below 5GHz. The diamond-shaped mapping technique, presented in [2], uses 50% LOs and a different I and Q combining method but suffers from nonlinearity due to a clipping operation. Besides, the large peak-to-average power ratio (PAPR) in modern wireless standards requires the DTX to operate in deep power back-off (DPBO), degrading its average efficiency. To target applications requiring large modulation bandwidth, high spectral purity and average efficiency, we present a DTX with a signed IQ interleaved upconversion approach based on 50%-LO clock distribution, which enables close to perfect orthogonal I/Q summation. To enhance its average efficiency, a compact, 4-way Doherty DPA architecture is introduced.

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One of the biggest challenges in modern transmitter (TX) design, when going from the fourth generation (4G) to fifth generation (5G) communications network, is to handle the increased linearity requirements without introducing any compromise in the energy efficiency of the TX line-up. In analog systems, high quality for the TX signal can be only achieved when using very linear operation of the (analog) power amplifier (PA). This severely limits the achievable efficiency in practical TX line-ups. Alternatively, a nonlinear PA can be used, which is linearized by digital pre-distortion (DPD) circuitry. This later approach is commonly used in (4G) macro-cell base stations, but it comes at the cost of increased system complexity and high supply power for the advanced DPD unit. When going towards 5G handset, or massive -multiple - input -multiple - output (mMIMO) 5G base station units, that facilitate beamforming and higher data rates to their end users. The required RF output power per individual transmitter is rather low (at most only a few watts). However, since many more transmitters are used in 5G applications (e.g. a factor 64 x to 256 x more than in 4G base stations) the use of an advanced DPD units in each individual TX-lineup, with their related high-power consumption becomes simply impractical. Consequently, to address these changing needs, it is highly desirable to find new circuit-level TX solutions, that overcome the traditional linearity-efficiency trade-off. To achieve this goal, this PhD work is focused on the utilization and tailoring of digital device operation, as facilitated by advanced CMOS technologies, towards the needs of modern wireless applications with their wideband complex modulated TX signals. The circuit techniques developed within this thesis, target an inherently linear amplitude-code-word (ACW) to TX output signal transfer, as such omitting completely the need for a power hungry advanced DPD unit, or alternatively, rely on a much more simple and consequently less power hungry DPD unit for the most demanding applications (e.g. when handling large modulation bandwidths). The circuit techniques developed in thesis, allow excellent drain and TX line-up efficiency, while being compatible with wideband efficiency enhancement techniques like Doherty. The proposed circuit techniques are also able to correct for process, voltage, load and temperature variations of the application.@en

This article presents the first application of a digital-intensive intrinsically linear digitally controlled class-E technique in a Doherty configuration. By careful nonlinear segmentation and multiphase RF-clocking along with overdrive-voltage control and automatic duty-cycle correction, it is shown that even the nonlinearities related to Doherty operation can be fully handled by the underlying design such that digital predistorion (DPD) can be, in principle, omitted. The nonlinearity behavior of the whole digital Doherty power amplifier (PA) is analyzed, and closed-form equations are given to predict the AM-AM and AM-phase modulation (PM) curves. In addition, time/phase mismatch between the peak and main branches and the AM and PM signals is accurately compensated. In order to achieve the maximum intrinsic linearity, two separate chips with the same architecture, but different design parameters, are fabricated as the main and peak amplifiers in 40-nm bulk CMOS. To achieve a large RF bandwidth and high passive combiner efficiency, a differential low-loss, wideband Marchand balun-based Doherty power combiner, implemented using reentrant coupled lines with independent second-harmonic control is proposed, and together with the matching network is fabricated on a two-layer PCB. The measured peak/6-dB power backoff P OUT, drain efficiency/power-added efficiency at 2.4 GHz are 17.5 dBm/12.2 dBm, 57%/52% and 36%/25% with VDD main/peak = 0.6 V/0.7 V. Measured results without using DPD show -41-dBc adjacent channel power ratio (ACPR) and -36-dB error vector magnitude (EVM) for a 16-MHz OFDM signal at 2.5 GHz. By using DPD, the measured ACPR and EVM of a 16-MHz/32-MHz OFDM signals are -52 dBc/-48 dBc and -50 dB/-48 dB, respectively.

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A fully integrated RFDAC based phase modulator in 40nm bulk CMOS is presented. To boost in-band linearity and the frequency range of operation, a harmonic rejection RFDAC architecture that suppresses the 3^rd and 5^th harmonics is proposed. The achieved frequency agility of the phase modulator is verified over a 0.6-2.5GHz range yielding EVM of -34.5dB and -36dB for an 18Mb/s and 75Mb/s GMSK signals, respectively. The power consumption of the proposed phase modulator is 33 mW at 2.4GHz.

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The maximum achievable linearity of a digital polar transmitter (DPTX) is mainly constrained by two RF-DAC associated nonidealities; namely, aliasing of sampling spectral replicas (SSR) of the AM and PM signals, and the presence of nonuniform quantization noise. In this work, using DPTX hardware linearization, in combination with PM SSR filtering and iterative learning control (ILC) algorithm improved by look-up tables (LUT), a CMOS DPTX is linearized close to its theoretical ACPR and EVM limits as predicted by its resolution. Using the ILC technique as underlying basis, an effective real-time direct-learning digital predistortion (DPD) technique is proposed. Measurement results show -60/-53 dBc ACPR and -60/-47 dB EVM using the ILC algorithm for 16/64 MHz OFDM signals, and -55/-48 dBc ACPR and -50/-44 dB EVM using the proposed DPD for 16/64 MHz OFDM signals. To the best of author's knowledge, this is the highest linearity reported for a DPTX operating with wideband signals.

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This paper presents a wideband linear direct-digital RF modulator (DDRM) in 40-nm CMOS technology. An innovative I/ Q-interleaving RF digital-to-analog converter (DAC) is proposed to enable the combination of in-phase (I) and quadrature (Q) signals in a more digital fashion, thereby improving the linearity performance at large bandwidths. The DDRM also features an advanced second-order hold digital interpolation filter to suppress the sampling spectral replicas in the presence of large bandwidth signals. Moreover, the harmonic rejection technique in the context of RF DAC operation is adopted and implemented. The 2 × 9-bit DDRM core occupies 0.21 mm 2 and consumes 110 and 146 mW at 1 and 3 GHz, respectively, with the peak power of +9.2 dBm. The error vector magnitude (EVM) and adjacent channel power ratio (ACPR) at 3 GHz for a 57-MHz 64-QAM signal are better than -30 and -45 dB, respectively, and ACPR remains as low as -44 dBc up to a wide bandwidth of 113 MHz.@en

To fully benefit from the progress of CMOS technologies, it is desirable to completely digitize the TX, replacing its final stage with a digitally controlled PA (DPA). The DPA consists of arrays of small sub-PAs that are digitally controlled to modulate the output amplitude, thus operating as an RF-DAC [1-6]. DPAs are normally designed in a switched mode (Classes E/D/D-1, etc.) to achieve high efficiency while using high sampling rate to attenuate and push the spectral images to higher frequencies. However, they suffer from high nonlinearity in their AM-code-word (ACW) to AM and ACW-to-PM conversion. To correct for such nonlinearities, digital pre-distortion (DPD) of the input signal is often used [1-3], typically implemented by look-up tables (LUT). Unfortunately, DPD approaches suffer from large signal-BW expansion due to their inherently nonlinear characteristics. This, combined with the already present BW regrowth in a polar TX in the AM and PM paths, yields significant hardware-speed/power constraints when the signal BW becomes large. For a Cartesian TX, the use of LUT-DPD is even more complicated since a full 2D LUT is typically required [2]. To relax the overall system complexity, it is highly desirable to have a PA with a maximum inherent linearity without compromising its power or efficiency. In this work, an ACW-AM correction based on nonlinear sizing along with controlling the peak voltage of RF clocks (overdrive voltage tuning) and a ACW-PM correction based on multiphase RF clocking are introduced to linearize the characteristic curves of a Class-E polar DPA with intent to avoid any kind of pre-distortion.@en

This paper presents an intrinsically linear wideband polar digital power amplifier (DPA) operating in semi class-E/F2 mode. Without using any type of digital pre-distortion (DPD), the proposed architecture achieves high linearity by accurately controlling its AM-AM and AM-PM characteristic curves through nonlinear sizing, overdrive-voltage control, and multiphase RF clocking without compromising the achievable output power or efficiency. Measurement results of the fabricated prototype in 40-nm bulk CMOS show -46 and -40 dBc adjacent channel power ratio (ACPR) for 20and 40-MHz orthogonal frequency-division multiplexing (OFDM) signals, respectively. The measured error vector magnitudes (EVM) are -36 dB and -33 dB, respectively. Measured results indicate a PSAT, peak drain efficiency (DE), and power-added efficiency (PAE) of 14.6 dBm, 44%, and 26%, respectively, using a 0.5-V supply for the output stage at 2.2 GHz.@en

This paper presents a wideband linear direct digital RF modulator (DDRM) in 40nm CMOS technology. It features an advanced 2nd-order-hold interpolation filter and I/Q-interleaving harmonic rejection RF DACs. The 2×9-bit DDRM core occupies 0.21mm2 and consumes only 110mW at 1 GHz. Within the 0.9-3.1GHz frequency range, the peak output power reaches +9.2dBm and the 3rd/5th harmonic rejection, C-IMD3, and OIP3 are respectively better than 30 dB, -44 dBc, and +25 dBm. The EVM and ACPR at 3 GHz for a 57-MHz 64-QAM signal are better than -30 dB and -45 dB, respectively, and ACPR remains as low as -44 dBc up to a wide bandwidth of 110 MHz.@en

This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is +21.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than -30 dB while the average drain efficiency is 24%.@en

A highly efficient and linear wideband digital polar CMOS class-E power amplifier (DPA) is presented. Using a compensated wideband Marchand balun with re-entrant coupled lines for the output matching network, more than 50% peak drain efficiency over 2.2-3GHz with 16-17dBm Pout are achieved. The linearity is significantly improved by nonlinearly sizing the DPA array along with overdrive-voltage control and concurrent multiphase RF clocking. The chip prototype is fabricated in 40nm bulk CMOS and the balun is fabricated on a two-layer PCB. Measured results show -40dBc for a 40MHz QAM signal at 2.6GHz without using any sort of DPD. The measured peak Pout, DE and PAE at 2.6GHz are 17.2dBm, 67% and 45% with VDD=0.7V.@en