A Fully-Integrated Digital-Intensive Polar Doherty Transmitter

Conference paper (2017)

Authors

Y. Shen Electronics - EEMCS
M. Mehrpoo OLD QCD/Charbon Lab
M. Hashemi Electronics - EEMCS
Michael Polushkin External organisation
Lei Zhou Ampleon Netherlands
M Acar Ampleon Netherlands
T.G.R.M. van Leuken Signal Processing Systems - EEMCS
S.M. Alavi Electronics - EEMCS
L.C.N. de Vreede Electronics - EEMCS
Research Group
Electronics (EEMCS) (TU Delft)
Efficiency enhancement Phase modulator DPD Doherty transmitter Digital-intensive polar On-chip combiner
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Published Date

2017

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

This paper presents an advanced 2.3-2.8 GHz fully-integrated
digital-intensive polar Doherty transmitter realized in 40nm standard
CMOS. The proposed architecture comprises CORDIC, digital delay
aligners, interpolators, digital pre-distortion (DPD) circuitry in
combination with frequency-agile wideband phase modulators followed by
the digital main and peak power amplifier (PA) operating in quasi-load
insensitive class-E using an on-chip power combiner. At 2.5 GHz, its
maximum output power is +21.4 dBm. Drain efficiency is 49.4% at peak
power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz
64-QAM signal, the measured EVM is better than -30 dB while the average
drain efficiency is 24%.

Files

07969051.pdf
(.pdf | 0.462 Mb)