Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD

Conference paper (2017)

Authors

M. Hashemi Electronics - EEMCS
Lei Zhou Ampleon Netherlands
Y. Shen Electronics - EEMCS
Mohammadreza Mehrpoo External organisation
L.C.N. de Vreede Electronics - EEMCS
Research Group
Electronics (EEMCS) (TU Delft)
Efficient Wideband CMOS Linear Class-E Digital PA DPD-less
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Published Date

2017

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

A highly efficient and linear wideband digital polar CMOS class-E power amplifier (DPA) is presented. Using a compensated wideband Marchand balun with re-entrant coupled lines for the output matching network, more than 50% peak drain efficiency over 2.2-3GHz with 16-17dBm Pout are achieved. The linearity is significantly improved by nonlinearly sizing the DPA array along with overdrive-voltage control and concurrent multiphase RF clocking. The chip prototype is fabricated in 40nm bulk CMOS and the balun is fabricated on a two-layer PCB. Measured results show -40dBc for a 40MHz QAM signal at 2.6GHz without using any sort of DPD. The measured peak Pout, DE and PAE at 2.6GHz are 17.2dBm, 67% and 45% with VDD=0.7V.

Files

08059066.pdf
(.pdf | 0.985 Mb)