This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency. To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency.

Many applications require wide bandwidth transmitters, but unfortunately, they usually have way less than 50% average drain efficiency for their modulated signals. This low efficiency is a significant drawback in all wireless applications, both for battery power devices and base stations. The Doherty radio frequency (RF) power amplifier architecture is widely used to enhance the average efficiency for modulated signals in base stations. Its popularity is due to its relatively cheap and simple hardware and its suitability to handle high-power wideband modulated signals. However, even Doherty amplifiers often have less than 50% average efficiency and are restricted in their RF bandwidth. This thesis reviews recent research on the Doherty power amplifier (DPA) topology and discusses possible power and bandwidth efficiency improvements. In the second part of the thesis, another topology is introduced, which also provides Doherty-like behavior. That topology is called a Pseudo Doherty Load Modulated Balanced Amplifier (PD-LMBA). The performance of PD-LMBA is compared with “conventional” DPAs. Circuit design examples of DPA and PD-LMBA are given. The thesis concludes with a PD-LMBA prototype design, which appears to be very promising in its wideband performance.