This paper presents a comprehensive investigation into novel Recurrent Neural Network (RNN) architectures for enhancing the efficiency and performance of Digital Predistortion (DPD) for Radio Frequency (RF) Power Amplifiers (PAs). The research first introduces Delta Just Another Network (DeltaJANET), a computationally efficient model that leverages a sparse delta update rule. By updating only a small fraction of the hidden state at each time step, DeltaJANET significantly reduces the complexity and computational cost associated with traditional RNNs, establishing a new baseline for efficient DPD solutions. Building upon this foundation of efficiency, the paper then proposes a second, more powerful architecture: the Temporal Convolutional Just Another Network (TC-JANET). This advanced hybrid model synergistically combines a Temporal Convolutional Network (TCN) for long-range feature extraction with a lightweight Just Another Network (JANET) unit. Key innovations, including a direct memory input module and a dynamic phase normalization scheme applied to the recurrent state, enable the TC-JANET to robustly model complex PA behaviors. A systematic multi-seed evaluation demonstrates the exceptional performance and scalability of this architecture, showing that it significantly surpasses existing benchmarks and establishing a new benchmark for high-performance DPD solutions.

The rapid growth of wireless data traffic is driving 6G networks toward higher data rates, lower latency, and wider bandwidths. Power amplifiers (PAs) must operate efficiently and linearly over extreme bandwidths, but traditional polynomial-based digital predistortion (DPD) techniques struggle with wideband signals due to increased computational complexity and memory requirements.
Neural network (NN)-based DPD offers a promising alternative, modeling complex PA nonlinearities with improved flexibility and linearization performance. Existing NN-based approaches, mostly using recurrent neural networks, face limitations in parallelization, making them unable to satisfy the throughput requirements of wideband signals.
This thesis introduces a hardware-aware Phase-Normalized Time-Delay Neural Network DPD architecture, optimized for FPGA and ASIC implementation. The design balances the high linearization performance and throughput requirements with low power consumption and minimal silicon area. The study used algorithm–hardware co-design strategies to create a viable NN-based DPD solution for next-generation wireless transmitters. The research is limited to simulated measurements, with no physical measurements being done.
Simulated results show that the PNTDNN achieves strong linearization for both narrowband and wideband signals, with FPGA and ASIC implementations supporting real-time processing of 20 MHz and 400 MHz base-band signals, respectively. The architecture demonstrates scalability, energy efficiency, and reprogrammability, providing a practical solution for next-generation 6G transmitters and bridging the gap between advanced NN-based DPD algorithms and hardware feasibility.
Simulated results demonstrate that the PNTDNN achieves strong linearization performance for both narrowband and wideband signals. For a 400 MHz baseband bandwidth signal, it attains –36.3 dB EVM, –38.5 dB NMSE, and –45.6 dB ACPRAVG with approximately 1000 parameters, while for a 20 MHz baseband bandwidth signal, it achieves –54.0 dB EVM, –48.2 dB NMSE, and –59.4 dB ACPRAVG using only 64 parameters. The FPGA implementation for the 20 MHz dataset achieves 7.5× oversampling at 170 MHz clock frequency and throughput, using 405 mW power. The ASIC implementation for the 400 MHz dataset achieves 2× oversampling at 1.2 GHz clock frequency and throughput, with an area of 0.451 mm2 using 893 mW power. Both the FPGA and ASIC implementations allow power optimization via unstructured pruning, with the FPGA having hardcoded weights and biases and the ASIC having reprogrammable weights and biases.

Eye tracking serves as a critical component across diverse areas of human-computer interaction (HCI) and healthcare applications, serving as a key enabler for intuitive and seamless user experiences. In HCI, eye tracking allows systems to detect users’ visual attention and gaze direction, facilitating natural interaction methods in augmented reality (AR), virtual reality (VR), and assistive technologies. In the healthcare domain, it is used for diagnosing and monitoring neurological disorders for patients. To be practical for deployment in wearable or embedded systems, eye tracking systems must deliver realtime performance while maintaining ultra-low power consumption. This requirement poses significant challenges in algorithm design and hardware implementation, especially when balancing accuracy, responsiveness, and energy efficiency. This thesis introduces JaneEye, an event-based eye tracking hardware accelerator optimized for ultralow latency and power consumption. The system is built around a lightweight, self-designed neural network architecture, in which a gated multilayer perceptron (MLP) and a novel convolutional Just Another Network (ConvJANET) layer play central roles in enabling efficient and accurate prediction. Despite having only 17.6K parameters, the proposed network maintains high prediction accuracy. Through software-hardware co-design strategies including quantization and nonlinear activation function approximation together with a new dataflow strategy that combines weight stationary and output stationary modes, the accelerator achieves remarkable performance. Based on post-layout simulation in GlobalFoundries 12LP-PLUS technolog, the JaneEye accelerator reaches an end-to-end latency of 0.5 ms (equivalent to 2000 FPS) while consuming just 18.9 μJ per frame operating at 400 MHz. To the best of our knowledge, this work demonstrates state-of-the-art trade-offs among accuracy, latency, and energy efficiency for event-based eye tracking, making it a strong candidate for integration into future AR/VR headsets and wearable healthcare devices.

In the field of Organ-on-Chip research, there is a desire to have an automatic and scalable system for muscle excitation and contraction measurement. In this thesis, the CHAMP is introduced, a 24-well system that uses magnets and Hall sensors to determine the deflection of cantilevers on which muscles are seated. The CHAMP allows for simultaneous four-channel measurements with a resolution in the micro-Newtons and milliseconds. The entire design can be put in an incubator, is biocompatible and 3D printed from rigid and flexible resins. The system can be read out and controlled via USB connection, with custom programs in CSV format for simple and automatic measurements. The excitation is a square wave, with variable parameters for duty cycle, frequency and amplitude in the common ranges. Future designs should replace the cantilever material to reduce nonlinearity and manufacturing problems, and improve the ADC resolution to enhance measurement accuracy.

The leisure vehicle industry has long trailed the main automotive sector in regards to driver assistance technologies, despite one-sided accidents at low speed being a common occurrence in the industry. This thesis describes the process of designing a wireless 360° camera sensing system in an attempt to catch up this leisure vehicle market to present automotive technology. Such systems can be found in many modern vehicles, however these systems are all wired implementations with there being no need for a wireless solution. The design emphasizes quick and straightforward calibration to facilitate usage as an aftermarket product. A prototype is built using Raspberry Pi's to demonstrate the feasibility of the design. This paper also presents research on possible further improvements of the designed system, and it presents a concept of a composite system through integration with a proximity sensing system.

As communication capacity continues to expand, the application of deep neural networks (DNNs) for digital pre-distortion (DPD) has become increasingly prominent in addressing non-linearity issues in wideband power amplifiers (PAs). The advent of the fifth-generation (5G) era imposes higher requirements on DPD regarding frequency and latency. The integration of multiple-input multiple-output (MIMO) technology and micro base stations has driven the trend towards low-power, small-area DPD chips. This paper presents a high-performance, Gated Recurrent Unit (GRU)-based hardware architecture, characterized by high parallelism, and low resource consumption, enabling real-time signal processing by DPD. A novel method is proposed, employing quantization-aware training (QAT) with Hardsigmoid and Hardtanh functions to quantize the floating-point model in software. The optimized algorithm is implemented on hardware with inter-layer pipelining and retiming to optimize timing and increase clock frequency. Additionally, hardware-efficient linear functions, Hardsigmoid and Hardtanh, are utilized for activation functions to minimize hardware overhead. Experimental results demonstrate that hardware implementation achieves an Adjacent Channel Power Ratio (ACPR) of 49.48 dBc and an Error Vector Magnitude (EVM) of 46.05 dB, showin minimal degradation compared to the floating-point model (49.58 dBc/ 46.70 dB). Simulated under 22nm CMOS technology, the DPD chip, operating at 2GHz, occupied an area of 0.047 mm2 and is capable of handling signals with bandwidth up to 70 MHz. The highest throughput reaches 256.5 GOp/s while the power efficiency reaches 1.3154 TOp/s/W.

With the advancement of 5G/6G radio networks, the demand for high-performance power amplifiers (PAs) with clean spectra and compact constellations has increased significantly. To address these challenges, Artificial Intelligence (AI)-based digital predistortion (DPD) has emerged as a promising approach to linearize radio-frequency (RF) PAs. However, existing state-of-the-art AI-based architectures rely on computationally expensive online feature extraction to achieve satisfying linearization performance, resulting in complicated algorithm data paths and difficulty in energy-efficient hardware implementation. This thesis proposes a new deep recurrent neural network (RNN)-based DPD architecture, called Skip Gated Recurrent Unit (SGRU), with precise offline baseband signal feature extraction to bypass the need for complex online feature extraction while still maintaining high linearization performance. The proposed RNN architecture employs the end-to-end (E2E) learning framework to implement an efficient DPD model. By combining the offline feature extraction and E2E framework, we achieved a more streamlined and faster training method for wideband RF power amplifier (PA) DPD. With a simplified neural network architecture and fewer parameters, our approach utilizes 394 parameters to achieve an adjacent channel power ratio (ACPR) (lower/upper) of -45.16/-44.31 dBc for 100 MHz orthogonal frequency division multiplexing (OFDM) signal, ACPR (lower/upper) of -38.44/-42.09 dBc for 200 MHz OFDM signal. Compared to previous state-of-art phase gated just-another-network (PG-JANET) [1] and decomposed vector rotation just-another-network (DVR-JANET) [2], our approach has better ACPR and error vector magnitude (EVM) performance with parameters around 400. Compared to vector decomposition long-short-term memory (VDLSTM) [3], our approach achieves a better lower/upper band balance.

Receivers for millimeter-wave (mm-wave) 5G, with the ability to detect a low-power desired signal, in the vicinity of large power blockers, require highly linear circuitry with a large power consumption. Suppressing the out-of-band blockers reduces this power consumption. N-path filters (NPFs) have recently been used to reject interferers in adjacent channels, by using a tunable center frequency. The state-of-the-art NPFs at mm-wave, however, only have a limited attenuation or use a large chip area. In this thesis, a fourth-order NPF is designed for 26-30 GHz. The implemented filter combines two frequency-shifted NPFs to create a flat in-band response and a steep roll-off, without the use of a large passive baseband filter. A rejection of 14 dB in the center of the first adjacent channel is obtained. This increases up to 24 dB at far-out-of-band frequencies. The noise figure of 10-12 dB is the lowest of the state-of-the-art, due to the added low-noise amplifier (LNA) in front of the filter. Despite this LNA, the designed filter achieves a comparable power consumption (40 mW) and smaller area (0.2-0.3 µm) than the state-of-the-art. The filter designed in this thesis is the first reported active N-path filter at mm-wave. The bandwidth is among the smallest reported, while the estimated area is lower than the state-of-the-art.

The goal of the WiECG project is to create a prototype device that makes it possible to perform a 12-lead ECG measurement on patients without wires from the patient to a monitor. The solution consists of a transmitter and receiver, one of which is close or on the patients body and the other is connected to a monitor.

This thesis describes the design and implementation of a subsystem of the prototype device that performs digitization, digital processing and reconstruction of the measured 12-lead ECG signal. This concerns converting nine 0 to 3.3V analog signals to the digital domain by using Analog-to-Digital converters, real-time filtering of nine signals with multiple digital IIR filters and reconstructing nine digital signals to the analog domain using Digital-to-Analog converters. Furthermore, component selection, design decisions and the implementation process will be detailed in this document.

The subsystem proposed in this paper is able to successfully sample, efficiently filter and reconstruct nine signals in real time. Recommendations on improving the implementation to better adhere to the lower power requirements for a longer battery life are provided as future research prospects.

Phase-locked loops (PLLs) are ubiquitous in many RF applications such as frequency synthesizers in wireline and wireless transceivers. In this project, a charge-sampling PLL has been designed, which employs a charge-domain sub-sampling phase detector. The high gain of the phase detector helps suppress the in-band phase noise, while the lowered duty cycle of the sampling reference clock results in reduced reference spurs. A current-starved ring oscillator has been designed to support an output frequency range of 1-2 GHz. In order to achieve the synthesis of fractional frequencies, a capacitive DAC based constant slope digital-to-time converter (DTC) has been designed. In order to calibrate the DTC gain (KDTC) over PVT variations, a digital background gain calibration loop has been introduced. The performance of the Fractional-N PLL is comparable to that of the state-of-the-art. In order to measure the PLL's performance in silicon, the design has been taped-out in TSMC 40-nm technology in July 2022.

In the ADome project, a truncated icosahedron is used as a frame for multiple antenna nodes. These nodes are used to measure the radiation pattern of an antenna-under-test located in the center of this dome. Since these antennas can be placed anywhere in the ADome by the user, a calibration system is necessary to find the spherical coordinates of each of these antennas.

In this thesis, a method is proposed that uses computer vision algorithms, written using the OpenCV library in C++, to locate each of these antennas by detecting controllable LEDs attached to the PCBs of the antenna nodes. The found pixel locations will then be used to get the spherical coordinates of the antennas with respect to the camera. Finally these spherical coordinates will be transformed to fit to the coordinate system of the ADome itself, by detecting landmarks in the form of fiducial markers which are located at predetermined locations.

The methods of recognition of the antennas within using computer vision are discussed, implemented and tested on real and simulated data. The accuracy of finding the antennas on the real data was within 2 pixels from the true location.

The methods regarding estimating the location of the antenna with respect to the camera are discussed next. These methods include a distortion estimation and correction, after which each pixel will get there corresponding spherical angles θ and φ. These methods are also tested on simulated and real data, where the accuracy on the real data falls within 0.5 degrees in comparison to the true data.

Finally the methods of transforming the spherical angle θ and φ of the antenna with respect to the camera, to the coordinate system of the ADome are discussed. This starts with a method of recognizing fiducial landmarks (landmarks are accurately known reference points), where in this research there is chosen for ArUco fiducials. After this, the location of these landmarks can be used to determine the location and orientation of the camera within the ADome. The method of finding the distances between each of the landmarks and the camera, is discussed and tested and has an accuracy of 2 cm. The method of finding the location of the camera, and the method of finding the orientation of the camera are discussed, however this has not been tested and fully implemented yet. With this location and orientation the location of an antenna can be easily determined.

In conclusion, this thesis is a good starting point for designing an Optical Calibration System, which could make determining the location of each of the antennas faster, and more accurate.

This thesis focuses on improving the readout of the ADome by implementing MCUs at each antenna probe, enabling local sampling and memory storage. The serial communication protocols CAN, SPI and I2C are considered and compared with one another. Ultimately, CAN is decided due to its robustness and simplicity which make the system cheap and ensures that the measurement will not get corrupted during transmission. Moreover, implementations of the new readout protocol are able to obtain measurement data store information at the local MCU. Test setups verification showed that antenna location can be stored and retrieved. Furthermore, the readout protocol is able to acquire multiple samples from the ADC locally.

The commercialization of millimeter wave frequencies for the 5G New Radio standard requires time and cost -effective testing equipment. The over-the-air measurement setup developed at the TU Delft (ADome) is able to reduce measurement time, by positioning multiple fixed sensing nodes around the antenna-under-test. To expand the system capabilities of the ADome, this work researches the possibilities of measuring signal quality by down-converting the high-frequency modulated signal to an intermediate frequency. This includes analysis on distributing the local oscillator to the sensing nodes, a proposed design and simulation of a passive single-balanced diode mixer circuit and simulated system EVM performance.

With the current advancements in quantum computing moving more circuitry into the cryogenic chamber there is a need for high-speed connectivity between the cryogenic and room temperature environment. Studies conducted to date have achieved high-speed links of multiple Gb/s utilizing a single CMOS chip at room temperature, yet a Cryo-CMOS wireline transmitter addresses a new topic in high-speed cryogenic electronic design necessary for the functioning and scale-up of quantum computers. This thesis entails the design of A DAC-based Cryo-CMOS 51.2 Gb/s PAM4 Wireline Transmitter. Overall, the proposed design is meant to demonstrate a high-speed signal generated by a Cyro-CMOS chip can be send through a cable from a cryogenic environment and received at room temperature. Requirements have been set up based on the measurement of the cable channel and simulation results showed these could be met with the designed circuitry. The system consists of a low-speed 16-to-1 serializing structure, a high-speed 4-to-1 Multiplexer, and a 6-bit (4b binary, 2b unary) CML DAC. The design is finished and taped out in 40-nm technology, however the chip is still in fabrication, so the results are based on simulation data only, in future research measurements will verify the working of the chip.

The objective of the bachelor graduation project detailed in this thesis is the development of a system suited for testing radio frequency (RF) power amplifiers (PAs). This PA test system is in particular set up for testing two-transistor interpolating-supply amplifiers.
Interpolating-supply PAs are efficiency-enhanced by employing multiple transistors supplied by different, fixed drain supply voltages, leading to different efficiency characteristics, which are then combined by switching between the transistors, resulting in an enchanced overal efficiciency. Turning on the right amplifying transistor takes place digitally by pre-adjusting the different data inputs or control of gate biases.
The PA test system is required to provide support for measurement and signal generation for 40 dBm output power of a 20 dB gain PA. Moreover, it is required to provide remote control access to the measurement equipment and automation of the tests, implemented in MATLAB.
The to-be-measured PA performance metrics were constrained to static tests for drain efficiency, power-added efficiency, AM/AM distortion, total harmonic distortion (THD) and intermodulation distortion (IMD).
In order to meet the requirements while making use of the available resources, it was recognized that the following subsystems were necessary:
• Baseband signal generation using a DAC;
• RF signal generation using a to-be-calibrated IQ modulator;
• Pre-amplifier, by own design; and
• Spectrum analyzer, controlled remotely.
The baseband signal generation subsystem was characterized with respect to noise and gain performance, which resulted in the making of noise-reducing LC low-pass filters. The provided IQ modulators were successfully calibrated for device non-idealities in an automated MATLAB GUI, allowing for clean RF signal generation. Three pre-amplifiers with over 27.5 dB power gain were realized for sufficient PA input power. A set of MATLAB functions and scripts for the spectrum analyzer and top-level control was written, enabling semi-automatic PA testing.
At the time of writing this thesis, the PA test system was put in use to characterize and evaluate two interpolating supply PAs. For automation, another GUI was implemented for the PA test system. The system proved to be able to determine PA input, output and DC power to measure the gain, linearity and efficiency in multiple static tests and for different PA bias conditions. Also THD and IMD for single-transistor were measured using the PA test system. The results were to a realistic extent similar to the simulated PA characteristics, aside from some anomalies which could possibly be explained by PA design implementation mistakes or test system nonidealities.