Charge-Sampling DTC based Fractional-N Phase-Locked Loop with Background DTC Gain Calibration

Master thesis (2022)

Authors

R. Gurbaxani Electrical Engineering, Mathematics and Computer Science

Contributors

M. Babaie Electronics - EEMCS (supervisor 1)
F. Sebastiano Quantum Circuit Architectures and Technology - EEMCS (supervisor 2)
L.C.N. de Vreede Electronics - EEMCS (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2022 Rishabh Gurbaxani
Phase-locked loop Fractional-N frequency synthesis Digital to time converter Digital background calibration Subsampling PLL
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Published Date

13-10-2022

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

Phase-locked loops (PLLs) are ubiquitous in many RF applications such as frequency synthesizers in wireline and wireless transceivers. In this project, a charge-sampling PLL has been designed, which employs a charge-domain sub-sampling phase detector. The high gain of the phase detector helps suppress the in-band phase noise, while the lowered duty cycle of the sampling reference clock results in reduced reference spurs. A current-starved ring oscillator has been designed to support an output frequency range of 1-2 GHz. In order to achieve the synthesis of fractional frequencies, a capacitive DAC based constant slope digital-to-time converter (DTC) has been designed. In order to calibrate the DTC gain (KDTC) over PVT variations, a digital background gain calibration loop has been introduced. The performance of the Fractional-N PLL is comparable to that of the state-of-the-art. In order to measure the PLL's performance in silicon, the design has been taped-out in TSMC 40-nm technology in July 2022.