Recent years have seen an exponential growth in required wireless data capacity. This exponential growth is expected to continue, while it is unsustainable if the power consumption associated with it will grow at the same rate. This calls for better power efficiency, which can usually be found in polar power amplifier architectures. This thesis focuses on the feasibility of a power RF-DAC, with as main focus to seek improvement in power efficiency. As all information up to the RF output is in the digital domain the design will be frequency agile, meaning that operation frequency is only dependent on the external matching network. As starting point an existing LDMOS technology is considered to implement a power Digital-to-RF-Amplitude Converter (DRAC) with a dedicated CMOS driver. As first demonstrator these two chips could be connected using flip-chip bonding. The proposed combination allows a maximum operation frequency of 3 GHz, providing a peak fundamental output power of 16,6 W with a drain efficiency of 64,4 % at the maximum operation frequency. Since the CMOS driver operates in Class-D a significantly lower average driver power consumption is expected compared to an analog system where a Class-A or Class-AB predriver would be used. This promising concept can change the way how future transmitters could be constructed. In conclusion a performance outlook will be given if a dedicated high power silicon technology that can feature the CMOS drivers would be available for 4G/5G applications.