A 10 Gbps Wireline Transceiver Link

To Interface Future RF-DACs

Master thesis (2020)

Authors

Y.J. Feng Electrical Engineering, Mathematics and Computer Science

Contributors

L.C.N. de Vreede Electronics - EEMCS (supervisor 1)
S.M. Alavi Electronics - EEMCS (supervisor 1)
D. Cavallo Tera-Hertz Sensing - EEMCS (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2020 Jun Feng
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Published Date

21-08-2020

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

This thesis presents the development of circuits and systems for fast wireline transceiver links that will enable a move towards highly integrable RF digital-to-analog converters.

A new perspective on the analysis of bit error rates in wireline links leads to the PAM spectral design space chart: a novel, visual system design analysis tool for PAM wireline circuit designers.

Moreover, a <2 mW/Gbps/lane, 10 Gbps wireline transmitter has been designed and taped-out in 40 nm CMOS. The proposed inherently pipelined 16:1 multiplexer and current mode logic driver design procedure are the key enablers for this performance.

Finally, for development of a 10 Gbps wireline receiver, a novel self-synchronized receiver design is proposed that removes the need of a classical clock and data recovery loop. At its core, this receiver comprises the design of a high-speed two-tail comparator and an asynchronous metastability detection loop.