A Quadrature Harmonic Rejection Voltage-Domain Mixer with 20 dBm OIP3 and 800 MHz IF Bandwidth
T. Ibrahim (TU Delft - Electronics)
M. R. Beikmirza (TU Delft - Electronics)
M.S. Alavi (TU Delft - Electronics)
LCN de Vreede (TU Delft - Electronics)
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Abstract
A wideband harmonic rejection voltage-domain mixer using resistive scaling is presented with excellent linearity and high IF bandwidth. Thin-oxide devices with constant gate-to-source voltages (VGS) are utilized to maximize the switching linearity. A novel switching core topology providing low-impedance IF outputs is proposed to support wideband in-phase (I) and quadrature (Q) mixer outputs when loaded by ADCs. Eight LO clock phases, each with a 25 % duty cycle, are on-chip generated for quadrature down-conversion and harmonic rejection (HR). By cleverly activating and organizing the mixer branches, the RF mixer input impedance can be kept perfectly constant throughout all eight clock phases, enhancing the mixer’s linearity. The TSMC 40 nm-CMOS realized mixer reaches 20.9 dBm OIP3 at an IF of 50 MHz with a conversion loss of 22.5 dB. It offers an 800 MHz 3-dB IF bandwidth at a differential capacitive loading of 0.15 pF, with a total power consumption of 40.7 mW drawn from a 1.1 V supply. The mixer targets linear wideband base station observation receiver applications.