Clock generation
Naser Pourmousavian (University College Dublin)
Teerachot Siriburanon (University College Dublin)
Feng-Wei Kuo (Taiwan Semiconductor Manufacturing Company (TSMC))
Masoud Babaie (TU Delft - Electronics)
Robert B. Staszewski (TU Delft - Electronics, University College Dublin)
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Abstract
In modern transceivers, clock generation and planning is one of the key aspects. As a matter of fact, with the increasing occupation of the spectrum and with the increasing use of discrete front ends, non-idealities such as reciprocal mixing are getting more and more critical. This chapter presents the different techniques to enhance the performance of the clock generation especially for all-digital phase locked loops (PLLs) (ADPLLs).
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