Clock generation

Pourmousavian, Naser; Siriburanon, Teerachot; Kuo, Feng-Wei; Babaie, Masoud; Staszewski, Robert Bogdan

Clock generation

Book chapter (2019)

Authors

Naser Pourmousavian University College Dublin

Teerachot Siriburanon University College Dublin

Feng-Wei Kuo Taiwan Semiconductor Manufacturing Company (TSMC)

Masoud Babaie Electronics

Robert Bogdan Staszewski Electronics, University College Dublin

Research Group

Electronics

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Published Date

2019

Language

English

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Research Group

Electronics

Abstract

In modern transceivers, clock generation and planning is one of the key aspects. As a matter of fact, with the increasing occupation of the spectrum and with the increasing use of discrete front ends, non-idealities such as reciprocal mixing are getting more and more critical. This chapter presents the different techniques to enhance the performance of the clock generation especially for all-digital phase locked loops (PLLs) (ADPLLs).

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