Ultra-low phase noise ADPLL for millimeter wave

Book chapter (2020)

Authors

Z. Zong Electronics - EEMCS
R.B. Staszewski Electronics - EEMCS , University College Dublin
Research Group
Electronics (EEMCS) (TU Delft)
Power consumption Phase noise Cmos digital integrated circuits Digital phase locked loops Field effect mimic Radio transceivers
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Published Date

2020

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).