Ultra-low phase noise ADPLL for millimeter wave

None, None; None, None

Ultra-low phase noise ADPLL for millimeter wave

Book Chapter (2020)

Author(s)

Zhirui Zong (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Robert Bogdan Staszewski (TU Delft - Electrical Engineering, Mathematics and Computer Science, University College Dublin)

Research Group

Electronics

Power consumption Phase noise Cmos digital integrated circuits Digital phase locked loops Field effect mimic Radio transceivers

DOI related publication

https://doi.org/10.1049/PBCS064E_ch13 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:099046dd-40d1-4148-ab8c-b7ac61f821a2

More Info

expand_more

Publication Year

2020

Language

English

Research Group

Electronics

Pages (from-to)

347-378

ISBN (electronic)

9781785618857

Downloads counter

226

Abstract

Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).