Ultra-low phase noise ADPLL for millimeter wave

Book Chapter (2020)
Author(s)

Z. Zong (TU Delft - Electronics)

Robert B. Staszewski (TU Delft - Electronics, University College Dublin)

Research Group
Electronics
DOI related publication
https://doi.org/10.1049/PBCS064E_ch13
More Info
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Publication Year
2020
Language
English
Research Group
Electronics
Pages (from-to)
347-378
ISBN (electronic)
9781785618857

Abstract

Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).

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