Addressing the advancement toward large-scale quantum computers, this article presents the first four-level pulse amplitude modulation (PAM4) wireline transmitter (TX) operating at cryogenic temperatures (CTs). With quantum computers scaling up toward thousands of quantum bits (qubits), but having too limited fidelity for robust operation, continuous rounds of quantum error correction (QEC) are necessary. However, QEC requires a large amount of data to be transferred from a cryogenic controller at 4 K to a classical processor at room temperature (RT). To bridge the gap, a high-speed data link between the quantum processor at CT and the classical counterpart at RT is needed. The proposed PAM4 TX architecture integrates a low-power 64:4 serializer structure, a high-speed 4:1 current-mode logic (CML) multiplexer, and a linear 6-bit digital-to-analog converter (DAC). Considering the challenges and benefits of CMOS operating at CTs, the TX architecture and circuitry are designed to exploit the maximum speed, while maintaining sufficient linearity. The fabricated 40-nm CMOS chip achieves a data rate of 40-Gb/s (36-Gb/s), an energy efficiency of 2.46 pJ/b (2.47 pJ/b), and 97.8% (96.6%) ratio of level mismatch (RLM) at CT (RT). While demonstrating an energy efficiency comparable to prior-art TXs in more advanced CMOS nodes at RT, the broad operating temperature of the proposed TX enables the required high-speed wireline link for large-scale quantum computers.

State-of-the-art quantum computers already comprise hundreds of cryogenic quantum bits (qubits), and prototypes with over 10k qubits are currently being developed. Such large-scale systems require local cryogenic electronics for qubit control and readout, leaving the digital controllers for algorithm execution and quantum error correction (QEC) at room temperature due to the limited cryogenic cooling budget. The entire process, including qubit readout, data transmission, QEC, and algorithm execution, should be completed well within the qubit decoherence time, thus requiring a low-power high-speed communication link between the cryogenic quantum processor and classical processor located at room temperature. To this end, this paper presents the first cryo-CMOS high-speed 4-level pulse amplitude modulation (PAM4) wireline transmitter. Thanks to a power-efficient serializing architecture driving a 6-bit digital-to-analog converter (DAC), the 40-nm CMOS chip achieves a data rate of 40 Gb/s PAM4 with an efficiency of 2.46pJ/b and a ratio of level mismatch (RLM) of 97.8% at 4.2 K. While demonstrating an energy efficiency comparable to state-of-the-art transmitters in more advanced CMOS nodes, the extremely wide temperature operating range (4.2 K - 300 K) will enable future large-scale quantum computers.

This article presents an efficient digital polar transmitter (DPTX) at mm-wave frequencies that exploit a novel N -way series Doherty combiner (SDC) to enhance its drain and system efficiency at deep power back-off (PBO). The proposed N -way SDC is scalable and can be implemented elegantly using N transformers and N-1 shunt capacitors. As a proof of concept, a four-way Doherty DPTX is realized with the proposed SDC in which four identical but independent digital phase modulators deliver a phase-modulated constant envelope signal to their corresponding digital power amplifiers to perform the required amplitude modulation. Fabricated in a 40nm CMOS process, the proposed DPTX occupies a core area of 1.1 mathrm {mm^{2}} and exhibits 18.7dBm saturated output power and <-40dBc LO feedthrough. It demonstrates a drain efficiency of 33%/36%/22% at 0/4.5/11.5dB PBO at a 29.5GHz carrier frequency. While transmitting a 300MHz 64-QAM OFDM signal with a peak-to-average power ratio of 10.7dB, the DPTX achieves 18%/8% average drain/system efficiency, -27.6dB error vector magnitude, and -27.5dBc adjacent channel leakage ratio. To the best of our knowledge, this work is the first reported mm-wave Doherty transmitter that includes the entire chain all the way from the binary data stream up to the modulated mm-wave output signal.

Fifth-generation (5G) mm-wave communication systems support high-order modulation schemes with large peak-to-average power ratios (PAPR). This demands transmitter (TX) operation in deep power back-off (PBO), thus degrading its average efficiency. Hence, several mm-wave Doherty PAs have been proposed [1], [3] to address this issue. However, the number of their peaking amplifiers (PAP) has been limited to two, mainly due to poor scalability, and high losses in the Doherty power combiner. Therefore, the efficiency enhancement was restricted to the 10dB PBO range. Furthermore, prior-art chiefly employed an analog class-AB amplifier for the main PA (PAM), degrading the system efficiency (SE) for two reasons. First, the conduction angle of an analog amplifier increases with a reduction of the drive signal amplitude, resulting in a Class-A-type efficiency roll-off that severely degrades the achievable PBO efficiency. Second, the output impedance of analog PAs is almost constant while the PAs' load significantly increases in PBO Doherty operation. This results in a load mismatch at PBO, degrading the PAs' gain and efficiency while giving rise to AM-AM and AM-PM distortion.