Quantum computers require large-scale error correction codes to circumvent the limited fidelity of physical qubits. However, current error decoders are either not scalable to practical code sizes or cannot meet the strict real-time decoding requirements. This work presents a novel decoder for stabilizer error correction codes that exploits hyperdimensional computing to offer an efficient hardware implementation for large-scale codes, thus achieving low latency and high throughput. Next to a universal approach for generating the necessary hypervectors, an efficient method specific to surface codes is devised. In this very first implementation, the proposed decoder outclasses popular graph-based decoders for small surface codes with depolarizing noise and efficiently scales to large codes, thus representing both a suitable solution for near-term real-time error correction and a promising alternative for future large-scale codes.

The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-threshold-voltage (LVT) DRAM at 4.2 K is up to 2 × more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 ,000 × , thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

The cryogenic electronic interface for quantum pro-cessors requires cryo-CMOS embedded memories that cover a wide range of specifications. The temperature dependence of device parameters, such as the threshold voltage, the gate/subthreshold leakage, and the variability, severely alters the memories' performance between room temperature (RT) and cryogenic temperatures (4.2K). To assess the best memory design for a given application, this paper benchmarks three custom DRAMs and a custom SRAM in 40-nm CMOS at 4.2 K and RT, e.g., identifying that, while the SRAM is more power efficient for moderate-to-high speeds at RT, the 2T DRAM performs better than SRAM and 3T DRAMs at 4.2 K.