A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS
R.A. Damsteegt (TU Delft - QuTech Advanced Research Centre, QCD/Sebastiano Lab)
Ramon Overwater (TU Delft - QuTech Advanced Research Centre, QCD/Sebastiano Lab)
M Babaie (TU Delft - QuTech Advanced Research Centre, TU Delft - Electronics)
Fabio Sebastiano (TU Delft - Quantum Circuit Architectures and Technology, TU Delft - QuTech Advanced Research Centre)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-threshold-voltage (LVT) DRAM at 4.2 K is up to 2 × more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 ,000 × , thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.