A Benchmark of Cryo-CMOS 40-nm Embedded SRAM/DRAMs for Quantum Computing
R.A. Damsteegt (QCD/Sebastiano Lab, TU Delft - QuTech Advanced Research Centre)
Ramon Overwater (TU Delft - QuTech Advanced Research Centre, QCD/Sebastiano Lab)
M Babaie (TU Delft - QuTech Advanced Research Centre, TU Delft - Electronics)
Fabio Sebastiano (TU Delft - Quantum Circuit Architectures and Technology, TU Delft - QuTech Advanced Research Centre)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
The cryogenic electronic interface for quantum pro-cessors requires cryo-CMOS embedded memories that cover a wide range of specifications. The temperature dependence of device parameters, such as the threshold voltage, the gate/subthreshold leakage, and the variability, severely alters the memories' performance between room temperature (RT) and cryogenic temperatures (4.2K). To assess the best memory design for a given application, this paper benchmarks three custom DRAMs and a custom SRAM in 40-nm CMOS at 4.2 K and RT, e.g., identifying that, while the SRAM is more power efficient for moderate-to-high speeds at RT, the 2T DRAM performs better than SRAM and 3T DRAMs at 4.2 K.