This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2 K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.

Silicon-based photodiodes with different topologies are designed and simulated using the Sentaurus Technology Computer-Aided Design (TCAD) tool. These topologies comprise i) a conventional device with a single n-well, ii-iii) two versions of a branched (interdigitated) structure with a regular well, iv-v) a ring-like well structure with two different contact configurations, and finally vi) a structure that has a well in the center of the device. Designed devices are simulated with incident light within various wavelengths from 0.6 μm to 0.7 μm. The effect of the reflection coefficients of anode and cathode contacts is also investigated. The ring-like structure is the most effective in producing the highest cathode current for a given input optical power. Doping type effects are inquired as well.

In this paper, total ionizing dose (TID) induced effects on OLED devices are investigated. Two fresh and one electrically stressed OLEDs were irradiated with Cobalt-60. Current-Voltage (I-V) and illumination measurements at different operation conditions were performed. The changes in both I-V characteristics and intensity behavior showcase the degree of immunity towards irradiation, making these devices particularly appealing for space applications.

Radiation tolerance of electronic devices and systems is mandatory for defence and space applications. In order to increase this tolerance for CMOS FETs, different layout techniques such as enclosed layout transistors (ELTs) can be employed. In this paper, a regular layout transistor is compared with two ELTs, which have square and octagonal shaped gates. For this purpose, a test circuit in 180 nm device technology has been designed and fabricated. Experimental comparison of the same size transistors with different layouts is performed in terms of the impact of process variations, and radiation tolerance. It is concluded that ELTs with different shapes behave similarly under radiation at least upto a dose of 1 Mrad. Furthermore, octagonal shaped ELTs are slightly less impacted from process variations in regard to square ELTs.

Conventional transistor models are unable to capture the electrical behavior of transistors at cryogenic temperatures. In this paper, a methodology has been developed to calibrate temperature dependence parameters of Berkeley Short-Channel Insulated Gate Field Effect Transistor Model (BSIM3). Rather than modifying BSIM3 equations, the algorithm only changes the values of relevant parameters through noniterative, analytic operations; therefore, it can be implemented in typical circuit simulation tools. Proposed methodology allows to estimate I_D-V_GS and I_D-V_DS curves of the transistors having different channel lengths and widths even under various operating voltages, including the body bias. The parameter extraction algorithm runs with a reasonable computation cost and can compute parameter sets for transistors at user-defined cryogenic conditions.

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal-oxide-semiconductor field-effect transistors (n-MOSFETs). The effects of the finger number, channel geometry, and biasing voltages have been tested during irradiation experiments. All Berkeley short-channel insulated gate field-effect transistor model (BSIM) parameters relevant to the transistor properties affected by TID have been modified in an algorithmic flow to correctly estimate the sub-threshold leakage current for a given dose level. The maximum error of the model developed is below 8%. A case study considering a five-stage ring oscillator is simulated with the generated model to show that the power consumption of the circuit increases and the oscillation frequency decreases around by 14%.

In this paper, a metal-oxide-semiconductor-field-effect-transistor modeling methodology for cryogenic conditions has been extensively verified through device measurements performed on a cryogenic probe station that was cooled by liquid nitrogen (-196 °C). The approach is valid for all operating regions (including the sub-threshold mode). The developed model can estimate I _D - V _GS and I _D-V _DS curves of transistors having different channel lengths and widths with an error of less than 5%. Statistical analysis of cryogenic measurements is used to introduce the variation levels around the nominal cryogenic operation to identify the impact of process variations at cryogenic conditions. Models adjusted to various temperatures between -196 °C and -40 °C have been developed for applications requiring different cryogenic operation conditions. Experimental data collected from a ring oscillator is employed to visualize the model performance in estimating the cryogenic characteristics of a typical integrated circuit. It is shown that the frequency of the ring oscillator is correctly simulated using the proposed cryogenic models.