A Cryo-CMOS PLL for Quantum Computing Applications

Journal Article (2023)
Authors

Jiang Gong (QCD/Sebastiano Lab, TU Delft - QCD/Babaie Lab, TU Delft - QuTech Advanced Research Centre)

E Charbon-Iwasaki-Charbon (Kavli institute of nanoscience Delft, TU Delft - Quantum Circuit Architectures and Technology, QCD/Sebastiano Lab, École Polytechnique Fédérale de Lausanne)

F. Sebasatiano (TU Delft - Quantum Circuit Architectures and Technology, TU Delft - QuTech Advanced Research Centre)

Masoud Babaie (TU Delft - Electronics, TU Delft - QuTech Advanced Research Centre)

Research Group
QCD/Babaie Lab
Copyright
© 2023 J. Gong, E. Charbon-Iwasaki-Charbon, F. Sebastiano, M. Babaie
To reference this document use:
https://doi.org/10.1109/JSSC.2022.3223629
More Info
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Publication Year
2023
Language
English
Copyright
© 2023 J. Gong, E. Charbon-Iwasaki-Charbon, F. Sebastiano, M. Babaie
Research Group
QCD/Babaie Lab
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. @en
Issue number
5
Volume number
58
Pages (from-to)
1362-1375
DOI:
https://doi.org/10.1109/JSSC.2022.3223629
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Abstract

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated analog PLL structure is used so as to maintain high performance from 300 to 4.2 K. The PLL incorporates a dynamic-amplifier-based charge-domain sub-sampling phase detector (PD), which simultaneously achieves low phase noise (PN) and low reference spur, thanks to its high phase-detection gain and minimized periodic disturbances on the voltage-controlled oscillator (VCO) control. Fabricated in a 40-nm CMOS process, the PLL achieves <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>78.4-dBc reference spur, 75-fs rms jitter, and 4-mW power consumption at 300 K when generating a 10-GHz carrier, leading to a <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>256.5-dB jitter-power FOM. At 4.2 K, the PLL synthesizes 9.4-to 11.6-GHz tones with an rms jitter of 37 fs and a reference spur of <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>69 dBc while consuming 2.7 mW at 10 GHz.

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