This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in weak inversion to achieve continuous operation from room temperature (RT) down to cryogenic temperatures. Their accuracy limitations due to curvature, body effect, and mismatch are investigated and experimentally validated. Implemented in 40-nm CMOS, the references show a line regulation better than 2.7%/V from a supply as low as 0.99 V. By applying dynamic element matching (DEM) techniques, a spread of 1.2% (3σ ) from 4.2 to 300 K can be achieved, resulting in a temperature coefficient (TC) of 111 ppm/K. As the first significant statistical characterization extending down to cryogenic temperatures, the results demonstrate the ability of the proposed architectures to work under cryogenic harsh environments, such as space- and quantum-computing applications.

The LinoSPAD2 camera combines a 512×1 linear single-photon avalanche diode (SPAD) array with an FPGA-based photon-counting and time-stamping platform, to create a reconfigurable sensing system capable of detecting single photons. The read-out is fully parallel, where each SPAD is connected to a different FPGA input. The hardware can be reconfigured to achieve different functionalities, such as photon counters, time-to-digital converter (TDC) arrays and histogramming units. Time stamping is performed by an array of 64 TDCs, with 20 ps resolution (LSB), serving 256 channels by means of 4:1 sharing. At sensor level, the pixel pitch is 26.2 μm with a fill factor of 25.1%. The median dark count rate of each SPAD at room temperature is below 100 cps at 6V excess bias, the single-photon timing resolution (SPTR) of each channel is 50 ps FWHM, and the peak photon detection probability reaches ~50% at 510 nm at the same excess bias. The fill factor can be increased by 2.3× by means of microlenses, with good spatial uniformity and flat spectral response above 400 nm. At system level, the average instrument response function (IRF) is 135 ps FWHM. The LinoSPAD2 camera enables a wide range of time-of-flight and time-resolved applications, including 3D imaging, fluorescence lifetime imaging microscopy (FLIM), heralded spectroscopy, and compressive Raman imaging, to name a few. Thanks to its features, LinoSPAD2 is a novel generation of reconfigurable single-photon image sensors capable of adapting their read-out and processing to match application-specific requirements, and combining SPAD arrays with advanced, massively-parallel computational functionalities.

This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration. The design is implemented in 40-nm CMOS technology and achieves 36.2-dB signal to noise and distortion ratio (SNDR) for Nyquist input at 4.2 K while maintaining a Walden figure of merit (FOM textsubscript W) of 200 pJ/conv-step (for a 10.8-mW power consumption), including the clock receiver, and 15 pJ/conv-step (for a 0.8-mW power consumption) for just the core ADC. With these specifications, the ADC can support the simultaneous readout of 20 qubit channels with a power consumption of 0.5 mW/qubit, thus advancing toward the full integration of the cryogenic readout for future large-scale quantum processors.

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated analog PLL structure is used so as to maintain high performance from 300 to 4.2 K. The PLL incorporates a dynamic-amplifier-based charge-domain sub-sampling phase detector (PD), which simultaneously achieves low phase noise (PN) and low reference spur, thanks to its high phase-detection gain and minimized periodic disturbances on the voltage-controlled oscillator (VCO) control. Fabricated in a 40-nm CMOS process, the PLL achieves <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>78.4-dBc reference spur, 75-fs rms jitter, and 4-mW power consumption at 300 K when generating a 10-GHz carrier, leading to a <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>256.5-dB jitter-power FOM. At 4.2 K, the PLL synthesizes 9.4-to 11.6-GHz tones with an rms jitter of 37 fs and a reference spur of <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>69 dBc while consuming 2.7 mW at 10 GHz.

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.

As big strides were being made in many science fields in the 1970s and 80s, faster computation for solving problems in molecular biology, semiconductor technology, aeronautics, particle physics, etc., was at the forefront of research. Parallel and super-computers were introduced, which enabled problems of a higher level of complexity to be solved. At about the same time, Nobel-laureate physicist Richard Feynman launched what seemed at the time a wild idea; to build a computer based on quantum physics concepts such as superposition and entanglement [1]. The outrageousness of his ideas is documented in the book 'Surely, You're Joking, Mr. Feynman' [2].

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50μW RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm ² and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a new PN expression for an oscillator is derived by considering the shot-noise effect. To reach the optimum performance of an LC oscillator, a common-mode (CM) resonance technique is implemented. Additionally, this work presents a digital calibration loop to adjust the CM frequency automatically at 4.2K, reducing the oscillator's PN and thus improving the control fidelity. The calibration technique reduces the flicker corner of the oscillator over a wide temperature range (10 $\times $ and 8 $\times $ reduction at 300K and 4.2K, respectively). At 4.2K, our 0.15-mm2 oscillator consumes a 5-mW power and achieves a PN of -153.8dBc/Hz at a 10MHz offset, corresponding to a 200-dB FOM. The calibration circuits consume only a 0.4-mW power and 0.01-mm2 area.

Quantum computers (QCs) promise significant speedup for relevant computational problems that are intractable by classical computers. QCs process information stored in quantum bits (qubits) that must be typically cooled down to cryogenic temperatures. Since state-of-the-art QCs employ only a few qubits, those qubits can be driven and read out by room-temperature electronics connected to the cryogenic qubits by only a few wires. However, practical QCs will require more than thousands of qubits, making this approach impractical due to system complexity and reliability concerns. Although frequency multiplexing would reduce the interconnects to room temperature by fitting many qubit channels in the same physical interconnect, an excessive number of interconnects would still be required. An alternative, more scalable solution is a cryogenic electronic interface operating very close to the quantum processor to keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnect to room temperature. This system must comprise drivers, readout circuits (LNAs, ADCs), and a digital controller to steer the quantum-algorithm execution [1]. While cryogenic CMOS (cryo-CMOS) wideband drivers and LNAs supporting qubit frequency multiplexing have been shown before [1] -[3], no wideband cryo-CMOS ADC has been demonstrated yet.

The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications¹. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)². When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’^3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots^7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm¹⁰, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.

In quantum computing (QC) systems, cryogenic electronic interfaces can address the scalability and sheer interconnect complexity of the control/readout of thousands of quantum bits (qubits) required to execute practical quantum algorithms [1]. As shown in Fig.1-top, a frequency synthesizer is one of the main building blocks of such a cryogenic CMOS (cryo-CMOS) controller. However, designing a cryo-CMOS PLL for QC applications presents several challenges. Firstly, <60 fsec integrated jitter (σj) is required to achieve a single-qubit gate fidelity of 99.999% [2]. Secondly, to control multiple qubits with a single cable, a frequency multiplexed controller demands <-60dBc reference spur (SREF) to avoid interfering with other qubits. Thirdly, as the dilution fridge cooling power is limited, a low power consumption (PDC) is necessary to simultaneously control more qubits. Finally, PLL must be extremely robust against PVT variations, as it operates at a physical temperature of 4.2K, where no mature models are available. To address those issues, we report the first cryo-CMOS PLL operating at 4.2K. It achieves 45fsrms jitter and-71dBc SREF by introducing a charge-mode sub-sampling PLL that incorporates a new phase detector (PD) based on dynamic-amplifiers' operation.

The neonatal brain is a vulnerable organ, and lesions due to hemorrhage and/or ischemia occur frequently in preterm neonates. Even though neuroprotective therapies exist, there is no tool available to detect the ischemic lesions. To address this problem, we have recently designed and built the new time-domain near-infrared optical tomography (TD NIROT) system – Pioneer. Here we present the results of a phantom study of the system performance. We used silicone phantoms to mimic risky situations for brain lesions: hemorrhage and hypoxia. Employing Pioneer, we were able to reconstruct accurately both position and optical properties of these inhomogeneities.

Blumino is the first analog silicon photomultiplier with integrated amplifier, comparator and time-To-digital converter (TDC). The combination of a photodetector together with on-chip readout circuitry enables system-level advantages, such as internal parasitic reduction, compactness and simplicity. The analog silicon photomultiplier has a third output, called fast terminal (FT), in addition to the anode and cathode, which is used for timing measurements. The analog silicon photomultiplier presents excellent photon detection efficiency greater than 40% at 420 nm, making it suitable for positron-emission tomography. Measurement results of the TDC indicate a resolution of 128 ps least significant bit (LSB) with a differential nonlinearity and integral nonlinearity of-1/+5 LSB and-2.4/+0.9 LSB, respectively. The discriminator comprises two preamplifier stages followed by a complementary self-biased differential amplifier stage which is coupled to the analog silicon photomultiplier's FT through a decoupling capacitor. The sensor is also fully backward-compatible through the standard output which can be coupled to dedicated ASICs and standard readout integrated circuits. In addition to the electrical, radiation, and optical performance, the integration of a custom CMOS analog silicon photomultiplier process with standard CMOS process was investigated.

Single-photon avalanche diode (SPAD) arrays can be used for single-molecule localization microscopy (SMLM) because of their high frame rate and lack of readout noise. SPAD arrays have a binary frame output, which means photon arrivals should be described as a binomial process rather than a Poissonian process. Consequentially, the theoretical minimum uncertainty of the localizations is not accurately predicted by the Poissonian Cramér-Rao lower bound (CRLB). Here, we derive a binomial CRLB and benchmark it using simulated and experimental data. We show that if the expected photon count is larger than one for all pixels within one standard deviation of a Gaussian point spread function, the binomial CRLB gives a 46% higher theoretical uncertainty than the Poissonian CRLB. For typical SMLM photon fluxes, where no saturation occurs, the binomial CRLB predicts the same uncertainty as the Poissonian CRLB. Therefore, the binomial CRLB can be used to predict and benchmark localization uncertainty for SMLM with SPAD arrays for all practical emitter intensities.

Quantum computers (QC) promise to solve certain computational problems exponentially faster than a classical computer due to the superposition and entanglement properties of quantum bits (qubits). Among several qubit technologies, spin qubits are a promising candidate for large-scale QC, since (1) they have a small footprint allowing them to be densely integrated and (2) they can operate at relatively high temperatures (\gt1\mathrm{K}) [1], potentially reducing system cost and complexity.

In preterm infants, there is a risk of life-lasting impairments due to hemorrhagic/ischemic lesions. Our time-domain (TD) near-infrared optical tomography (NIROT) system “Pioneer” aims at detecting both disorders with high spatial resolution. Successfully tested on phantoms, “Pioneer” entered the phase of improvements and enhancements. The current probe (A-probe) was adapted for an optoacoustics instrument. A new probe (B-probe) optimized for TD measurements is required. Our aim is to determine the optimal arrangement of light sources in the B-probe to increase the sensitivity and the resolution of Pioneer and to improve the ability of the system to detect both ischemia and hemorrhage. To do this, we simulated TD-NIROT signals in NIRFAST, a MATLAB-based package used to model near-infrared light propagation through tissue. We used 16 × 16 detector array, with ~2.2 mm distance between the detectors. Light sources were arranged around the field of view (FoV). We performed forward simulations of light propagation through a “homogeneous case” (HC) tissue (μ′_s = 5.6 cm⁻¹, μ_a = 0.07 cm⁻¹). Next, we simulated light propagation through “inhomogeneous case” -tissue’ (IC) tissue by adding ischemia (μ_a = μ_a · 2.5 cm⁻¹) or hemorrhage (μ_a = μ_a · 50 cm⁻¹) to HT as a spherical inclusion of 5 mm radius at different depths in the FoV center and identified the source location that provides the higher contrast on the FoV: max_i ∈ I (FoVContrast_SOURCE). It was found that sources located closer to the FoV center generate greater contrast for late photons. This study suggests the light sources in B-probe should be closer to the FoV center. The higher sensitivity is expected to lead to a higher image quality.

This article describes the challenges and opportunities encountered in designing an electronic interface for quantum processors. It focuses on the use of standard CMOS technology to design and fabricate integrated circuits (ICs) operating at cryogenic temperatures. The article also focuses on spin qubits possibly operated in the high milli-Kelvin or even in the low Kelvin domain. To realize a spin qubit, a single electron is isolated in an extremely small site on the surface of a semiconductor die. A large magnetic field is applied to ensure that the spin-up and spin-down states of the electron correspond to distinct energy levels. Those two states are then used to encode the qubit quantum states.

Fluorescence molecular tomography (FMT) emerges as a powerful non-invasive imaging tool with the ability to resolve fluorescence signals from sources located deep in living tissues. Yet, the accuracy of FMT reconstruction depends on the deviation of the assumed optical properties from the actual values. In this work, we improved the accuracy of the initial optical properties required for FMT using a new-generation time-domain (TD) near-infrared optical tomography (NIROT) system, which effectively decouples scattering and absorption coefficients. We proposed a multimodal paradigm combining TD-NIROT and continuous-wave (CW) FMT. Both numerical simulation and experiments were performed on a heterogeneous phantom containing a fluorescent inclusion. The results demonstrate significant improvement in the FMT reconstruction by taking the NIROT-derived optical properties as prior information. The multimodal method is attractive for preclinical studies and tumor diagnostics since both functional and molecular information can be obtained.

Quantum computers require classical electronics to ensure fault-tolerant operation. To address compactness and scalability, it was proposed to implement such electronics as integrated circuits operating at cryogenic temperatures close to those at which quantum bits (qubits) operate. Circulators are among the most common blocks used in the qubit readout chain, but they are currently discrete devices with a bulky footprint, thus preventing large-scale system integration. For this reason, we present here a detailed description of the first fully integrated CMOS circulator operating from 300 K down to 4.2 K to be an integral part of cryogenic quantum computing platforms. At 300 K, the circuit's operating frequency is centered around 6.5 GHz with 28% fractional bandwidth, and it has 2.2-dB insertion loss, 2.4-dB noise figure, and 18-dB isolation while consuming 2.5-mW core power. These results are achieved thanks to a fully passive architecture based on LC all-pass filters, which allows achieving a 1.6\times increase in fractional bandwidth and the lowest power consumption with respect to the state of the art while using only 0.45 mm² of core area. This allows miniaturization of circulators in power-constrained multi-qubit readout systems.