High speed imagers find applications in many fields such as scientific and medical imaging, automotive applications, machine vision and much more. In this thesis, the design of a high speed, high dynamic range (HDR) CMOS sensor with electronic global shutter (GS) and flexible exposure control is presented. The sensor is designed in the 0.11μm CIS process, features 1k(H) x 1k(V) pixels and achieves frame rates greater that 10.000 fps.A review of the architecture of the sensor is given, along with functional illustrations for each comprising block. The quadrant-based approach is described, along with the selectable region-of-interest capability. The pixel design is a eleven-transistor (11T) pinned photodiode global shutter pixel, implementing HDR by means of two in-pixel capacitors. The design of the pipelined Sample & Hold, column gain and column-level Correlated Double Sampling (CDS) circuits are shown.

Constant increase in data processing efficiency has enabled, among many other things, the intensive use of depth mapping technologies. Consumer applications, such as gaming, augmented and virtual realities (AR/VR), and other human-machine interfaces, are typically based on intensive image processing, either by triangulation and/or structured light, which has limitations on speed, resolution, range, and robustness to background noise. On the other hand, TOF depth sensing has been investigated in the academic and industrial engineering communities for several years, as an alternative to solve such restrictions, and few products are emerging. Direct time-of-flight (dTOF), specifically, requires more elaborate detectors and data processing, but it has the potential of reaching much longer distances at higher speed and accuracy, with the advantage of being robust to high background noise, making it suitable for space, automotive and consumer applications. One known drawback of dTOF, however, is data volume. For instance, automotive applications require over 100m range, only few centimeters accuracy, and multiple measurements for a reasonable precision, which produce data rates that can reach tens or even hundreds of Gbps, in large sensors, thus setting processing constraints to even very efficient GPUs, as well as chip readout capability. It is essential to provide as much on-chip processing as possible, in order to reduce data throughput, thus reducing power consumption and speeding up processing time. Some architectures have been proposed attempting to solve this problem, but the required memory renders them only feasible for an SiPM, single-pixel approach. Another known issue with light detection and ranging (LiDAR) is regarding the interference of multiple systems on each other. A software-based approach has been implemented, but requiring intensive post-processing resources. In this thesis, a novel approach for on-chip processing is proposed. With the use of cutting-edge 3D-stacking technologies, more flexibility and computational power can be spent on the chip, while not compromising fill factor. A novel proposal for dealing with external interferes is introduced, as well as novel phase/frequency locking solution at the sensor level, as a reference for timing measurements. @en

If a practical quantum computer is to be built, it will not only need quantum programming languages and qubits, but hardware-software interfaces as well. These interfaces, also known as computer (micro)architectures are the key to creating a ’quantum stack’, where a programmer can directly execute programs onto quantum hardware. A functional quantum computer microarchitecture, the Central Controller-Light (CCLight), has been designed, implemented on a Field Programmable Gate Array (FPGA), and verified to control superconducting qubits successfully. The next logical step, in hopes of creating a more scalable quantum computing system, is to take the CCLight and implement it as an Application-Specific Integrated Circuit (ASIC). In this thesis, the CCLight was built into an ASIC. It was shown that this approach yields the potential for higher performance and lower power for the microarchitecture core, and the groundwork for more robust and automatic testing of similar microarchitectures was laid out. Lastly, the lack of scalability in the original approach, wherein the processor transmits multi-byte codewords to the analog/RF hardware controlling the qubits, was revealed.

Positron Emission Tomography (PET) is one of the most relevant medical imaging techniques utilized for cancer detection and tumor staging. The success of PET relies on the high sensitivity and accuracy to detect and quantify molecular probe concentrations, in the order of picomole/liter. Although there are several positron-emitting molecular probes available, the 18F-fludeoxyglucose (18F-FDG) contributes remarkably to the high PET specificity and sensitivity. Since the success of PET imaging is strongly connected to the 18F-FDG, this imaging technique is also known as FDG-PET. In FDG-PET imaging three elements are key: - the molecular probe, - a PET scanner, - and an image reconstruction algorithm. The molecular probe is the contrast enhancement agent, which is administrated to the patient and absorbed by the target volumes. The emitted radiation produced by electron-positron annihilation is detected by the PET scanner, and the detection information is utilized to reconstruct a volumetric probe distribution. In essence, a PET scanner is a large acquisition system composed of thousands of channels that detect coincident gamma-photons generated during electron-positron annihilations. Typically, a single detection channel is composed of a scintillation material and a photodetector. The scintillation material absorbs the gamma-energy and emits light photons that produce digital or analog signals in the photodetectors. Nowadays, novel silicon-based photodetectors known as silicon photomultipliers (SiPMs) have been adopted as the next-generation photodetectors for PET applications. In order to further improve the FDG-PET molecular sensitivity and specificity, next-generation instrumentation requires a more accurate time estimation of the detected gamma-photon. Since in time-of-flight (TOF) PET the reconstructed images have an improved signal-to-noise ratio (SNR), which depends on the gamma-photon timemark precision. Additionally, increasing the detection sensitivity improves the statistical quality of information utilized during the image reconstruction process. This thesis introduces the basic concepts of molecular imaging and the key elements of FDG-PET in chapters 1 and 2. A comprehensive theoretical analysis on the utilization of the scintillation light information for gamma-photon timemark estimation is presented in chapter 3. Several estimation methods, such as maximum-likelihood estimation (MLE) and best linear unbiased estimation (BLUE) are presented, as well as a performance comparison with respect to the Cramér-Rao lower bound. Additionally, a detailed study is performed to determine the conditions that allow to reach the Cramér-Rao lower bound. Currently, FDG-PET imaging equipment is not equally available worldwide and one of the reasons is the high costs involved. Often, the design and implementation of TOF-PET instrumentation requires application specific integrated circuit (ASIC) designs, which increases the complexity of the design and required long prototyping phases. Chapter 4 describes the design, implementation, and characterization of TOF-PET instrumentation based on off-the-shelf components, configurable time-to-digital converters (TDCs) implemented on field-programmable gate arrays (FPGAs), and analog SiPMs (A-SiPMs). The proposed solution achieves TOF precision with a full-flexible, fast-prototyping, and ASIC-less designs. Recently, digital SiPMs (D-SiPMs) emerged as a next-generation photodetector for PET applications. In particular, the multichannel digital SiPM (MD-SiPM) architecture integrates single-photon avalanche diodes (SPADs), TDCs, and a readout logic into a monolithic CMOS photodetector. This type of photodetector confines all the measurement devices and circuits within an integrated solution. Therefore, it allows a direct system integration of a large number of channels since only digital signals are required for its operation. However, D-SiPM research and development requires long development and integration cycles due to the high complexity involved. Chapter 5 describes an individual building block and full-system comprehensive analysis of a monolithic array of 18x9 MD-SiPMs. Additionally, it describes in detail the methods developed for multiple TDC systems. In chapter 6, the system integration of MD-SiPMs for building PET detector modules is explained. The challenges of utilizing complex photodetectors for building PET modules, attachment of scintillator matrices, and digital readout strategies are described in a comprehensive manner. Finally, a conclusion of the PET technologies investigated throughout this thesis is given. In addition, an outlook of newer detection methods based on Cherenkov-PET and the corresponding requirements and eventual advantages is discussed.@en

Voltage references are one of the fundamental building blocks for designing any analog processing circuit. It serves as a reference for Analog to Digital Converters (ADCs), Digital to Analog Converters (DACs), power/voltage regulators and other measurement and control circuits. The performance of all these circuits cannot be better than the performance of the reference. Hence, it is very important that the voltage reference is very robust and performs reliably under process, supply, temperature or noise variations (PVT & N). Today, with the development of scalable quantum computing, there is a need for such a reference operating at cryogenic temperatures. Currently, the state of the art quantum circuits operates at ∼20 mK. To process and control the information flow, to and from these quantum processors, one requires an analog circuit to operate as close as possible to the quantum circuit, so as to make the full system scalable and more reliable since no line interconnect to room-temperature electronics would be required. As a step towards that idea, it is desired to push the operating temperature of the classical circuits as low as 4 K where enough cooling power is available without disturbing the operation of the quantum circuit. One of the basic blocks to be shifted to cryogenic temperatures is the voltage reference circuit. This thesis presents a systematic design of such a cryogenic voltage reference block, taking into account the device and circuit performance at 4 K. The targeted specifications are comparable to the references designed for standard industrial temperature range (233 K to 400 K). However, it is designed to work over an extremely wide temperature range (4 K to 400 K) to understand how far one can stretch the circuits designed with conventional CMOS. Two different variants of references are presented with the simulated performance of both over the industrial temperature range. A novel approach towards higher-order compensation is also presented which is expected to perform better than conventional CMOS reference over a wide range. To test their performance over the entire operating range (4 K to 400 K) and verify the designs, a tape-out is planned for October 2019.

The quantum bits (qubits) at the core of any quantum computers are so fragile that quantum error correction(QEC) schemes are needed to increase their robustness and enable fault-tolerant quantum algorithms. The surface code is one of the most popular QEC schemes, but it requires the availability of an efficient decoder. While neural networks have been shown to be well suited to this task, only software implementations have been studied in prior work. These have shown that neural network decoders can be on par or better than other decoding algorithms, but lack the required speed when running as software. The aim of this thesis is to investigate the hardware implementation of the neural networks for the decoders of surface codes to achieve the required speed. Most electronic hardware employed in quantum computers today operates at room temperature and is connected by bulky wires to the qubits, which are placed in a cryogenic chamber for proper operation. Since any useful quantum computer will comprise thousands or even millions of qubits, this work proposes to also move the QEC hardware to cryogenic temperatures (4 K). However, because at these temperatures the cooling power of cryogenic refrigerators is limited, the hardware needs to be low power, while ensuring enough speed to keep the pace of the QEC. The exploration of this work sweeps multiple parameters of a feed-forward neural network to find what the influence is on the decoder performance and the delay, the power, and the area. The parameters that are swept are the number of hidden layers, their sizes, the type of transfer functions and the number of bits used in the quantization of the weights and outputs. The results show that using the configurations found in this work it is possible to meet the performance and timing constraints using cryo-CMOS on both an FPGA and in a 40-nm technology. Although there are still some limitations in this work, such as the scaling in the power consumption and decoding performance for larger distances, there are multiple proposed improvements, making this is a stepping stone towards a future scalable implementation of QEC.

In today's digital life, security and encryption are becoming more and more important. As random number generators are a fundamental block of security and encryption, it is crucial to guarantee that these devices operate securely. Random numbers are usually generated in two ways; pseudo random number generators (PRNGs) and true random random number generators (TRNGs). PRNGs output a sequence based on a seed and a mathematical function. The deterministic nature of pseudo RNG devices can result in the PRNG not being applicable for all protocols, in which case TRNGs are needed. Almost all strong cryptography requires TRNGs to generate keys. The difference is that these devices instead rely on real world physics in order to generate a random number. The TRNG implementation explored in this thesis makes use of the quantum mechanical properties of photons. TRNGs making use of this principle of elementary quantum mechanical decision making are called quantum random number generators (QRNGs). This source of entropy provided by photons can be extracted by utilizing SPADs. QRNG devices based on SPADs have been made before in different ways, however there are still large grounds undiscovered when concerning SPAD based designs. As SPAD based QRNGs can be completely produced using CMOS technology, a world of possibilities open, including integration with already existing designs. Different aspects of SPAD QRNG designs will be discussed in this thesis; size, speed, hybrid designs and QRNG test-benching. The first part of the exploration focuses on creating an as small as possible QRNG. This resulted in a QRNG design which is as small as just one flip-flop and one SPAD, which is the smallest QRNG at the time of writing to the authors knowledge. Simulations show that the device is able to run up to 25 Mb/s using a SPAD with low deadtime. This device has been produced using 140nm technology by STMicroelectronics. The second part of the exploration, delves into how fast a SPAD based QRNG can be. The main goals here were to make the fastest possible QRNG with good scalability characteristics. This resulted in a design proposition based on the difference in the time of flight of two photons. This design is simulated using Matlab, and can reach 70 Mb/s per SPAD-duo depending on the deadtime of the SPAD used. When using a SPAD with a deadtime of 1us, the scaled up design needs only 16% of the SPADS needed by a state-of-the-art SPAD based QRNG design based on simulations. The amount of SPADs needed however schales almost linearly with a lower deadtime, having the potential to need only a fraction of the SPADs needed by the state-of-the-art in order to reach the same speeds. Then the concept of hybrid devices is explored, making use of a combination of PRNG and QRNG systems. The first hybrid design proposed is a design in which a very small QRNG is used to generate the key for multiple secure PRNG systems. The PRNG system used in this design is a trivium stream cypher. The design is completely written in VHDL except for the external QRNG. It then has been compiled and simulated using ModelSim, again using 140nm technology by STMicroelectronics. This resulted in a design which is able to reach speeds of 640 Gb/s, while using a total area of 99936 um2. The second hybrid device proposes a LFSR based design, which makes use of multiple very small QRNG devices to influence the function that the LFSR implements in order to increase the security. The last part of the exploration explores how it can be made easier and faster to test QRNG designs in an early design stage more accurately. As the source of entropy is quantum, the only risk of affecting the randomness is purely in which form the data of the photons is processed. By creating a chip which is able to extract the time of flight and the exact location of where the photon hit, testing potential QRNG devices can already be done in an early design stage with real-time data. A part of the chip that measures the time of flight of the photons arriving, has been designed in 40nm technology by STMicroelectronics. This part is a novel counter based on the principle of Gray counting, and is simulated extensively using extracted layout simulations. These simulations show that the device is able to run at speeds up to 3.6 GHz.

Quantum computers are able to deal with large problems, like molecular modelling, financial prediction and cryptography. A classical controller is used to control the qubits of the quantum computer. A proposed controller, operating at 4K, needs a clean voltage supply in order to function well. The long interconnects between the room temperature power supplies and the 4K classical controller are not loss-less and do have parasitic capacitance and inductance. Low drop-out (LDO) voltage regulators are able to clean this dirty supply voltage and produce a stable, regulated voltage. Therefore, a cryogenic 40nm CMOS LDO voltage is designed. This regulated is designed with room temperature models and optimized for operating at 4K. The specification are competitive to other LDO voltage regulators.