A 2.7mW 45fs_rms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications

Abstract

In quantum computing (QC) systems, cryogenic electronic interfaces can address the scalability and sheer interconnect complexity of the control/readout of thousands of quantum bits (qubits) required to execute practical quantum algorithms [1]. As shown in Fig.1-top, a frequency synthesizer is one of the main building blocks of such a cryogenic CMOS (cryo-CMOS) controller. However, designing a cryo-CMOS PLL for QC applications presents several challenges. Firstly, <60 fsec integrated jitter (σj) is required to achieve a single-qubit gate fidelity of 99.999% [2]. Secondly, to control multiple qubits with a single cable, a frequency multiplexed controller demands <-60dBc reference spur (SREF) to avoid interfering with other qubits. Thirdly, as the dilution fridge cooling power is limited, a low power consumption (PDC) is necessary to simultaneously control more qubits. Finally, PLL must be extremely robust against PVT variations, as it operates at a physical temperature of 4.2K, where no mature models are available. To address those issues, we report the first cryo-CMOS PLL operating at 4.2K. It achieves 45fsrms jitter and-71dBc SREF by introducing a charge-mode sub-sampling PLL that incorporates a new phase detector (PD) based on dynamic-amplifiers' operation.