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E. Charbon-Iwasaki-Charbon
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Quantum computers can provide exponential speedup in solving certain computational problems pertaining to drug discovery, cybersecurity, weather forecasting, etc. Although a quantum computer with just 50-qubits has been shown to surpass the computing power of the best supercomputers in specific applications, millions of qubits would be required for useful practical applications. One of the biggest obstacles in scaling from 50 qubits to millions of qubits is the interconnect bottleneck between solid-state qubits operating at 20 milliKelvin inside a dilution refrigerator and control electronics outside the dilution refrigerator connected via long coaxial cables. A 50-qubit processor requires hundreds of cables, digital to analog converters, mixers and amplifiers, clearly challenging the scalability of the system. The goal of this research is to build scalable quantum computers by operating CMOS control electronics inside the dilution refrigerator in proximity to quantum processors. The dissertation covers a broad aspect of cryogenic integrated circuit design spanning across devices, circuits and systems.
...
Quantum computers can provide exponential speedup in solving certain computational problems pertaining to drug discovery, cybersecurity, weather forecasting, etc. Although a quantum computer with just 50-qubits has been shown to surpass the computing power of the best supercomputers in specific applications, millions of qubits would be required for useful practical applications. One of the biggest obstacles in scaling from 50 qubits to millions of qubits is the interconnect bottleneck between solid-state qubits operating at 20 milliKelvin inside a dilution refrigerator and control electronics outside the dilution refrigerator connected via long coaxial cables. A 50-qubit processor requires hundreds of cables, digital to analog converters, mixers and amplifiers, clearly challenging the scalability of the system. The goal of this research is to build scalable quantum computers by operating CMOS control electronics inside the dilution refrigerator in proximity to quantum processors. The dissertation covers a broad aspect of cryogenic integrated circuit design spanning across devices, circuits and systems.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'.
In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator.
Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended.
In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K.
We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures.
One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law. ...
In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator.
Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended.
In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K.
We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures.
One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law. ...
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'.
In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator.
Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended.
In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K.
We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures.
One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator.
Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended.
In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K.
We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures.
One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
In conventional applications, such as bio-imaging and microscopy, SPAD is typically used as a single-photon counter. However, this advantage has been challenged by other photon-counting technologies, especially from CMOS-based QIS. Comparatively, apart from single-photon counting capability, QIS is superior to SPAD in terms of intrinsic multi-photon counting capability, quantum efficiency, dark noise, pixel size and fill factor. All these features indicate a low cost and high resolution photon counting imager can be built with QIS, which can be a great competition to SPADs. Moreover, QIS has been demonstrated with 1Mjot array, 0.175e- rms read noise and 1000 fps at less than 20 mWpower consumption.
...
In conventional applications, such as bio-imaging and microscopy, SPAD is typically used as a single-photon counter. However, this advantage has been challenged by other photon-counting technologies, especially from CMOS-based QIS. Comparatively, apart from single-photon counting capability, QIS is superior to SPAD in terms of intrinsic multi-photon counting capability, quantum efficiency, dark noise, pixel size and fill factor. All these features indicate a low cost and high resolution photon counting imager can be built with QIS, which can be a great competition to SPADs. Moreover, QIS has been demonstrated with 1Mjot array, 0.175e- rms read noise and 1000 fps at less than 20 mWpower consumption.
Design of a Quantum Microarchitecture Integrated Circuit
For Deep Cryogenic Operation
Master thesis
(2018)
-
Lizzy Hatfield, Edoardo Charbon, Koen Bertels, Ryoichi Ishihara, Carmina García Almudever, Fabio Sebastiano
If a practical quantum computer is to be built, it will not only need quantum programming languages and qubits, but hardware-software interfaces as well. These interfaces, also known as computer (micro)architectures are the key to creating a ’quantum stack’, where a programmer can directly execute programs onto quantum hardware. A functional quantum computer microarchitecture, the Central Controller-Light (CCLight), has been designed, implemented on a Field Programmable Gate Array (FPGA), and verified to control superconducting qubits successfully. The next logical step, in hopes of creating a more scalable quantum computing system, is to take the CCLight and implement it as an Application-Specific Integrated Circuit (ASIC). In this thesis, the CCLight was built into an ASIC. It was shown that this approach yields the potential for higher performance and lower power for the microarchitecture core, and the groundwork for more robust and automatic testing of similar microarchitectures was laid out. Lastly, the lack of scalability in the original approach, wherein the processor transmits multi-byte codewords to the analog/RF hardware controlling the qubits, was revealed.
...
If a practical quantum computer is to be built, it will not only need quantum programming languages and qubits, but hardware-software interfaces as well. These interfaces, also known as computer (micro)architectures are the key to creating a ’quantum stack’, where a programmer can directly execute programs onto quantum hardware. A functional quantum computer microarchitecture, the Central Controller-Light (CCLight), has been designed, implemented on a Field Programmable Gate Array (FPGA), and verified to control superconducting qubits successfully. The next logical step, in hopes of creating a more scalable quantum computing system, is to take the CCLight and implement it as an Application-Specific Integrated Circuit (ASIC). In this thesis, the CCLight was built into an ASIC. It was shown that this approach yields the potential for higher performance and lower power for the microarchitecture core, and the groundwork for more robust and automatic testing of similar microarchitectures was laid out. Lastly, the lack of scalability in the original approach, wherein the processor transmits multi-byte codewords to the analog/RF hardware controlling the qubits, was revealed.
Coincidence time resolution (CTR) in time-of-flight (TOF) positron emission tomography (PET) determines the signal-to-noise ratio (SNR) in iterative image reconstruction algorithms. In PET detectors, the photodetector's single-photon timing resolution (SPTR) influences the CTR by adding uncertainty to the single photoelectron time-of-arrivals. This effect can be modelled as the convolution of the scintillation pulse shape function and the total photodetector jitter at single-photon level, before following an order statistics process. Particularly in Cherenkov-based PET detectors, SPTR has a direct impacton the CTR due to the low number of detected photons. In this thesis, the research is focussed on the design of low thresh-old comparators for two specific purposes in PET. Firstly, the design of in-pixel (SPAD-cell) low-threshold comparator that improves SPAD jitter at the pixel level, since it allows the detection of photo-electron triggered avalanche at the earliest possible time, thus minimizing statistical fluctuations. The design is targeted for Cherenkov-based PET, where improvement in SPTR directly results in improvement of CTR. Secondly, for the integration of analog silicon photomultiplier (A-SiPM) on-chip. Such integration helps in realizing a high Photon Detection Effciency (PDE) and low Dark Count Rate (DCR) A-SiPM with integrated readout electronics. A high speed comparator with a direct connection to the fast terminal of A-SiPM has been realized.
...
Coincidence time resolution (CTR) in time-of-flight (TOF) positron emission tomography (PET) determines the signal-to-noise ratio (SNR) in iterative image reconstruction algorithms. In PET detectors, the photodetector's single-photon timing resolution (SPTR) influences the CTR by adding uncertainty to the single photoelectron time-of-arrivals. This effect can be modelled as the convolution of the scintillation pulse shape function and the total photodetector jitter at single-photon level, before following an order statistics process. Particularly in Cherenkov-based PET detectors, SPTR has a direct impacton the CTR due to the low number of detected photons. In this thesis, the research is focussed on the design of low thresh-old comparators for two specific purposes in PET. Firstly, the design of in-pixel (SPAD-cell) low-threshold comparator that improves SPAD jitter at the pixel level, since it allows the detection of photo-electron triggered avalanche at the earliest possible time, thus minimizing statistical fluctuations. The design is targeted for Cherenkov-based PET, where improvement in SPTR directly results in improvement of CTR. Secondly, for the integration of analog silicon photomultiplier (A-SiPM) on-chip. Such integration helps in realizing a high Photon Detection Effciency (PDE) and low Dark Count Rate (DCR) A-SiPM with integrated readout electronics. A high speed comparator with a direct connection to the fast terminal of A-SiPM has been realized.
In order to improve the ability to design digital ICs for cryogenic temperatures, the objective of this work is to characterize the timing performance of standard cells in the TSMC 40nm technology at a temperature range between 4K and 300K. A design was made to perform automated on-chip characterization of standard cell propagation delay, that makes use of random sampling. An ASIC was implemented and fabricated based on this design. A test setup was designed and build to perform the characterization. Besides that a design for a scalable gray-counter was developed and implemented that promises excellent performance for power critical applications.
...
In order to improve the ability to design digital ICs for cryogenic temperatures, the objective of this work is to characterize the timing performance of standard cells in the TSMC 40nm technology at a temperature range between 4K and 300K. A design was made to perform automated on-chip characterization of standard cell propagation delay, that makes use of random sampling. An ASIC was implemented and fabricated based on this design. A test setup was designed and build to perform the characterization. Besides that a design for a scalable gray-counter was developed and implemented that promises excellent performance for power critical applications.
With the advances towards a quantum computer incorporating many qubits, the demand for a scalable readout and control platform rises. Recent proposals for such a platform exploit the maturity of CMOS technology, to implement the various analog, RF and digital circuits required. To allow for scaling, the electronics that constitute this platform are translated close to the qubits in a cryogenic environment. Limited power dissipation can be absorbed in this environment, stressing the need for low-power circuits. Presently, digital control is carried out by FPGAs due to the rapidly changing control parameters. FPGAs are expected to be replaced in the future by ASICs, as they are inferior in terms of performance, area and most critically power dissipation. Conventional standard cells used for digital ASIC implementation are expected to be sub-optimal with respect to low-power and cryogenic operation, due to a shift in device characteristics in this environment. This thesis proposes the first minimal standard cell library designed for this environment, with low-power operation in mind, that enables future digital and mixed-signal designs to address the requirements demanded by the cryogenic environment.
...
With the advances towards a quantum computer incorporating many qubits, the demand for a scalable readout and control platform rises. Recent proposals for such a platform exploit the maturity of CMOS technology, to implement the various analog, RF and digital circuits required. To allow for scaling, the electronics that constitute this platform are translated close to the qubits in a cryogenic environment. Limited power dissipation can be absorbed in this environment, stressing the need for low-power circuits. Presently, digital control is carried out by FPGAs due to the rapidly changing control parameters. FPGAs are expected to be replaced in the future by ASICs, as they are inferior in terms of performance, area and most critically power dissipation. Conventional standard cells used for digital ASIC implementation are expected to be sub-optimal with respect to low-power and cryogenic operation, due to a shift in device characteristics in this environment. This thesis proposes the first minimal standard cell library designed for this environment, with low-power operation in mind, that enables future digital and mixed-signal designs to address the requirements demanded by the cryogenic environment.
The aim of this research is to explore the potential advantages of SPAD imagers used in microscopy. An ideal microscopy detector requires high sensitivity (high quantum efficiency QE or photon detection probability PDP), photon counting operation, low noise (dark current or dark count rate), timing resolution in the order of 100 ps, frame rate higher than 10 fps, a large enough pixel resolution and wavelength resolvability.
...
The aim of this research is to explore the potential advantages of SPAD imagers used in microscopy. An ideal microscopy detector requires high sensitivity (high quantum efficiency QE or photon detection probability PDP), photon counting operation, low noise (dark current or dark count rate), timing resolution in the order of 100 ps, frame rate higher than 10 fps, a large enough pixel resolution and wavelength resolvability.
In today's digital life, security and encryption are becoming more and more important. As random number generators are a fundamental block of security and encryption, it is crucial to guarantee that these devices operate securely. Random numbers are usually generated in two ways; pseudo random number generators (PRNGs) and true random random number generators (TRNGs). PRNGs output a sequence based on a seed and a mathematical function. The deterministic nature of pseudo RNG devices can result in the PRNG not being applicable for all protocols, in which case TRNGs are needed. Almost all strong cryptography requires TRNGs to generate keys. The difference is that these devices instead rely on real world physics in order to generate a random number. The TRNG implementation explored in this thesis makes use of the quantum mechanical properties of photons. TRNGs making use of this principle of elementary quantum mechanical decision making are called quantum random number generators (QRNGs). This source of entropy provided by photons can be extracted by utilizing SPADs. QRNG devices based on SPADs have been made before in different ways, however there are still large grounds undiscovered when concerning SPAD based designs. As SPAD based QRNGs can be completely produced using CMOS technology, a world of possibilities open, including integration with already existing designs. Different aspects of SPAD QRNG designs will be discussed in this thesis; size, speed, hybrid designs and QRNG test-benching. The first part of the exploration focuses on creating an as small as possible QRNG. This resulted in a QRNG design which is as small as just one flip-flop and one SPAD, which is the smallest QRNG at the time of writing to the authors knowledge. Simulations show that the device is able to run up to 25 Mb/s using a SPAD with low deadtime. This device has been produced using 140nm technology by STMicroelectronics. The second part of the exploration, delves into how fast a SPAD based QRNG can be. The main goals here were to make the fastest possible QRNG with good scalability characteristics. This resulted in a design proposition based on the difference in the time of flight of two photons. This design is simulated using Matlab, and can reach 70 Mb/s per SPAD-duo depending on the deadtime of the SPAD used. When using a SPAD with a deadtime of 1us, the scaled up design needs only 16% of the SPADS needed by a state-of-the-art SPAD based QRNG design based on simulations. The amount of SPADs needed however schales almost linearly with a lower deadtime, having the potential to need only a fraction of the SPADs needed by the state-of-the-art in order to reach the same speeds. Then the concept of hybrid devices is explored, making use of a combination of PRNG and QRNG systems. The first hybrid design proposed is a design in which a very small QRNG is used to generate the key for multiple secure PRNG systems. The PRNG system used in this design is a trivium stream cypher. The design is completely written in VHDL except for the external QRNG. It then has been compiled and simulated using ModelSim, again using 140nm technology by STMicroelectronics. This resulted in a design which is able to reach speeds of 640 Gb/s, while using a total area of 99936 um2. The second hybrid device proposes a LFSR based design, which makes use of multiple very small QRNG devices to influence the function that the LFSR implements in order to increase the security. The last part of the exploration explores how it can be made easier and faster to test QRNG designs in an early design stage more accurately. As the source of entropy is quantum, the only risk of affecting the randomness is purely in which form the data of the photons is processed. By creating a chip which is able to extract the time of flight and the exact location of where the photon hit, testing potential QRNG devices can already be done in an early design stage with real-time data. A part of the chip that measures the time of flight of the photons arriving, has been designed in 40nm technology by STMicroelectronics. This part is a novel counter based on the principle of Gray counting, and is simulated extensively using extracted layout simulations. These simulations show that the device is able to run at speeds up to 3.6 GHz.
...
In today's digital life, security and encryption are becoming more and more important. As random number generators are a fundamental block of security and encryption, it is crucial to guarantee that these devices operate securely. Random numbers are usually generated in two ways; pseudo random number generators (PRNGs) and true random random number generators (TRNGs). PRNGs output a sequence based on a seed and a mathematical function. The deterministic nature of pseudo RNG devices can result in the PRNG not being applicable for all protocols, in which case TRNGs are needed. Almost all strong cryptography requires TRNGs to generate keys. The difference is that these devices instead rely on real world physics in order to generate a random number. The TRNG implementation explored in this thesis makes use of the quantum mechanical properties of photons. TRNGs making use of this principle of elementary quantum mechanical decision making are called quantum random number generators (QRNGs). This source of entropy provided by photons can be extracted by utilizing SPADs. QRNG devices based on SPADs have been made before in different ways, however there are still large grounds undiscovered when concerning SPAD based designs. As SPAD based QRNGs can be completely produced using CMOS technology, a world of possibilities open, including integration with already existing designs. Different aspects of SPAD QRNG designs will be discussed in this thesis; size, speed, hybrid designs and QRNG test-benching. The first part of the exploration focuses on creating an as small as possible QRNG. This resulted in a QRNG design which is as small as just one flip-flop and one SPAD, which is the smallest QRNG at the time of writing to the authors knowledge. Simulations show that the device is able to run up to 25 Mb/s using a SPAD with low deadtime. This device has been produced using 140nm technology by STMicroelectronics. The second part of the exploration, delves into how fast a SPAD based QRNG can be. The main goals here were to make the fastest possible QRNG with good scalability characteristics. This resulted in a design proposition based on the difference in the time of flight of two photons. This design is simulated using Matlab, and can reach 70 Mb/s per SPAD-duo depending on the deadtime of the SPAD used. When using a SPAD with a deadtime of 1us, the scaled up design needs only 16% of the SPADS needed by a state-of-the-art SPAD based QRNG design based on simulations. The amount of SPADs needed however schales almost linearly with a lower deadtime, having the potential to need only a fraction of the SPADs needed by the state-of-the-art in order to reach the same speeds. Then the concept of hybrid devices is explored, making use of a combination of PRNG and QRNG systems. The first hybrid design proposed is a design in which a very small QRNG is used to generate the key for multiple secure PRNG systems. The PRNG system used in this design is a trivium stream cypher. The design is completely written in VHDL except for the external QRNG. It then has been compiled and simulated using ModelSim, again using 140nm technology by STMicroelectronics. This resulted in a design which is able to reach speeds of 640 Gb/s, while using a total area of 99936 um2. The second hybrid device proposes a LFSR based design, which makes use of multiple very small QRNG devices to influence the function that the LFSR implements in order to increase the security. The last part of the exploration explores how it can be made easier and faster to test QRNG designs in an early design stage more accurately. As the source of entropy is quantum, the only risk of affecting the randomness is purely in which form the data of the photons is processed. By creating a chip which is able to extract the time of flight and the exact location of where the photon hit, testing potential QRNG devices can already be done in an early design stage with real-time data. A part of the chip that measures the time of flight of the photons arriving, has been designed in 40nm technology by STMicroelectronics. This part is a novel counter based on the principle of Gray counting, and is simulated extensively using extracted layout simulations. These simulations show that the device is able to run at speeds up to 3.6 GHz.
The thesis presents a design that implements digitization of an analog SiPM's fast output on chip realized in order to minimize the complexity and increase the photon detection granularity. The design comprises a time-to-digital converter (TDC) in 0.35um CMOS technology. The TDC is a multi-path gated ring oscillator with a 6 bit counter for coarse bits and 9 phase detectors for the fine bits. Schematic and post-layout simulations indicated a 65ps LSB in the typical corner with a DNL of +/-0.55LSB and an INL of +/-1LSB. The TDC design does not comprise any additional calibration circuitry.
...
The thesis presents a design that implements digitization of an analog SiPM's fast output on chip realized in order to minimize the complexity and increase the photon detection granularity. The design comprises a time-to-digital converter (TDC) in 0.35um CMOS technology. The TDC is a multi-path gated ring oscillator with a 6 bit counter for coarse bits and 9 phase detectors for the fine bits. Schematic and post-layout simulations indicated a 65ps LSB in the typical corner with a DNL of +/-0.55LSB and an INL of +/-1LSB. The TDC design does not comprise any additional calibration circuitry.
Doctoral thesis
(2013)
-
FGA Quarati, Pieter Dorenbos, Freek Beekman, Catherine Pappas, Edoardo Charbon, F Camera, S Brandenburg, A Owens