A 2¹¹-1 pseudo-random binary sequence (PRBS) generator with trigger synchronization output (9.77-MHz rate) is implemented using synthetic transmission lines for the clock distribution. The full-rate data sequence is sourced from a 2:1 multiplex of dual shift register outputs synchronized to a half-rate clock. Quadrature half-rate clocks generated by a dual-mode (Dynastat) divide-by-2 are distributed via the synthetic lines to optimize power-speed tradeoffs in the design. The 790×620μm² PRBS designed in 130-nm SiGe BiCMOS (200/280 GHz f_T/fmax) consumes 250 mA at 2.5 V (i.e., 625 mW).

This book describes the digitally intensive time-domain architectures and techniques applied to millimeter-wave frequency synthesis, with the objective of improving performance and reducing the cost of implementation. Coverage includes system architecture, system level modeling, critical building block design, and digital calibration techniques, making it highly suitable for those who want to learn about mm-wave frequency generation for communication and radar applications, integrated circuit implementation, and time-domain circuit and system techniques. Highlights the challenges of frequency synthesis at mm-wave band using CMOS technology Compares the various approaches for mm-wave frequency generation (pros and cons) Introduces the digitally intensive synthesizer approach and its advantages Discusses the proper partitioning of the digitally intensive mm-wave frequency synthesizer into mm-wave, RF, analog, digital and software components Provides detailed design techniques from system level to circuit level Addresses system modeling, simulation techniques, design-for-test, and layout issues Demonstrates the use of time-domain techniques for high-performance mm-wave frequency synthesis.