The LinoSPAD2 camera combines a 512×1 linear single-photon avalanche diode (SPAD) array with an FPGA-based photon-counting and time-stamping platform, to create a reconfigurable sensing system capable of detecting single photons. The read-out is fully parallel, where each SPAD is connected to a different FPGA input. The hardware can be reconfigured to achieve different functionalities, such as photon counters, time-to-digital converter (TDC) arrays and histogramming units. Time stamping is performed by an array of 64 TDCs, with 20 ps resolution (LSB), serving 256 channels by means of 4:1 sharing. At sensor level, the pixel pitch is 26.2 μm with a fill factor of 25.1%. The median dark count rate of each SPAD at room temperature is below 100 cps at 6V excess bias, the single-photon timing resolution (SPTR) of each channel is 50 ps FWHM, and the peak photon detection probability reaches ~50% at 510 nm at the same excess bias. The fill factor can be increased by 2.3× by means of microlenses, with good spatial uniformity and flat spectral response above 400 nm. At system level, the average instrument response function (IRF) is 135 ps FWHM. The LinoSPAD2 camera enables a wide range of time-of-flight and time-resolved applications, including 3D imaging, fluorescence lifetime imaging microscopy (FLIM), heralded spectroscopy, and compressive Raman imaging, to name a few. Thanks to its features, LinoSPAD2 is a novel generation of reconfigurable single-photon image sensors capable of adapting their read-out and processing to match application-specific requirements, and combining SPAD arrays with advanced, massively-parallel computational functionalities.

Single-photon avalanche diode (SPAD) arrays are solid-state detectors that offer imaging capabilities at the level of individual photons, with unparalleled photon counting and time-resolved performance. This fascinating technology has progressed at a very fast pace in the past 15 years, since its inception in standard CMOS technology in 2003. A host of architectures have been investigated, ranging from simpler implementations, based solely on off-chip data processing, to progressively “smarter” sensors including on-chip, or even pixel level, time-stamping and processing capabilities. As the technology has matured, a range of biophotonics applications have been explored, including (endoscopic) FLIM, (multibeam multiphoton) FLIM-FRET, SPIM-FCS, super-resolution microscopy, time-resolved Raman spectroscopy, NIROT and PET. We will review some representative sensors and their corresponding applications, including the most relevant challenges faced by chip designers and end-users. Finally, we will provide an outlook on the future of this fascinating technology.

Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <100 mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.

Quantum computers enable a massive speed-up in calculations, thanks to the nature of quantum operations. To unlock quantum computation, a classical system infrastructure is required for the control of qubits and processing of their data. While qubits are generally operating at extremely low temperatures, the implementation of such a control interface is especially challenging for large scale systems, requiring significant physical interconnects between room temperature and the quantum devices. A cryogenic control interface is beneficial due to the closer qubit proximity, reduced thermal heat load, and potentially the integration with qubits at a single temperature. The basis for any such control interface is the error-correction loop, required for a longer coherence time of the qubits. The data processing, in the digital domain, can be completely implemented on an FPGA, operating at cryogenic temperatures. We report on the performance of FPGAS from Altera and Xilinx operating at cryogenic temperatures. A Cyclone V and Artix 7 were implemented on dedicated PCBs and extensive logic characterization was executed to investigate performance changes from room temperature towards 4 Kelvin. According to our extensive and systematic analysis, the Cyclone V is limited in operation down to 30 K, whereas the Artix 7 is fully functional down to 4 K.

To enable scalable quantum computers, it has been proposed that the quantum–classical interface has to be integrated and operated at deep-cryogenic temperatures. Common to all electronics is the power management and distribution through the system. These systems are currently powered from room temperature supplies, thus requiring long interconnects. This results in a significant and fluctuating voltage drop from the supply to the electronics. Especially sensitive systems, such as analog-to-digital and digital-to-analog converters that are needed for the read-out and control of the quantum processor, are thus limited in performance by the stability of the voltage regulation at room temperature. In this paper, we propose the design and use of voltage regulators at cryogenic temperatures (down to 4 K), close to the actual load. As no commercial regulator was found to work below 90 K, we implemented an ad hoc low-dropout regulator with commercially available components that operate at 4 K. Its output voltage varies with less than 0.2% over the complete temperature range and it can regulate loads within 1 mV/A.

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a significant reduction in current gain and a substantial increase in the base resistance. On the contrary, MOS devices show more stable performance even down to 4 K, but accurate device characterization for the design of such a circuit is currently missing. We present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16- \mu \text{m} CMOS technology. These results demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-&#x03BC;m and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device DC characteristics, the accuracy and validity of the compact models are demonstrated by comparing time-and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier (LNA), with the measurements at 4 K.

Electronics, from basic sub-micron MOSFETS to large-scale FPGAs, has been shown to operate at deep-cryogenic temperatures. Any digital system relies on an accurate clock for operation. While a clock signal can be provided from room temperature into the cryogenic environment, a clock generated at low temperatures features both smaller system size and tighter integration with the remainder of the electronics. While custom integrated cryogenic oscillator architectures have been proposed, mainly for the generation of radio-frequency signals, no commercial devices have been shown to operate at temperatures as low as 4 K. In this work, we focus on cryogenic frequency generation with commercially available oscillators. Eight commercial crystal and MEMS oscillators, generating 50 or 100 MHz signals, were tested over a wide temperature range from 300 K down to 4 K. Although MEMS devices suffered from apparent ageing effects after several cooling cycles, the majority of crystal oscillators were fully functional even at such low temperatures. The oscillation frequency of crystal-based devices decreased by roughly 0.1%, while power consumption and signal amplitude were slightly higher at cryogenic temperatures. The phase noise and corresponding phase jitter were elevated mainly due to increased flicker noise; the best device shows a phase jitter increase from 350 fs at 300 K to 620 fs at 4 K.

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.

Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.

Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.

Quantum computing holds the promise to achieve unprecedented computation power and to solve problems today intractable. State-of-the-art quantum processors consist of arrays of quantum bits (qubits) operating at a very low base temperature, typically a few tens of mK, as shown in Fig. 15.5.1 The qubit states degrade naturally after a certain time, upon loss of quantum coherence. For proper operation, an error-correcting loop must be implemented by a classical controller, which, in addition of handling execution of a quantum algorithm, reads the qubit state and performs the required corrections. However, while few qubits (∼10) in today's quantum processors can be easily connected to a room-temperature controller, it appears extremely challenging, if not impossible, to manage the thousands of qubits required in practical quantum algorithms [1].

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency (maximum 400 MHz), up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 6 bit resolution (ENOB) over a 0.9 to 1.6 V input range and an effective resolution bandwidth (ERBW) of 15 MHz. This implies that the ADC has an effective Nyquist rate of 30 MHz, with an oversampling ratio of $40\times $. The system non-linearities are less than 1 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform.

This paper presents the cryogenic characterization of the bipolar substrate PNPs that are typically employed as sensing elements in CMOS integrated temperature sensors. PNPs realized in a standard 160-nm CMOS technology were characterized over the temperature range from 7 K to 294 K. Although PNP non-idealities, such as finite current gain and parasitic base resistance, deteriorate at lower temperature, device operation similar to room temperature is observed down to 70 K, while operation at lower temperatures is limited by carrier freeze-out in the base region and limited current gain. These results demonstrate the feasibility of temperature sensors in standard CMOS at cryogenic temperature.