Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a significant reduction in current gain and a substantial increase in the base resistance. On the contrary, MOS devices show more stable performance even down to 4 K, but accurate device characterization for the design of such a circuit is currently missing. We present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16- \mu \text{m} CMOS technology. These results demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.

@en

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device DC characteristics, the accuracy and validity of the compact models are demonstrated by comparing time-and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier (LNA), with the measurements at 4 K.

@en

The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.

@en

Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.@en