Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.

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The design of a large-scale quantum computer requires co-optimization of both the quantum bits (qubits) and their control electronics. This work presents the first systematic design of such a controller to simultaneously and accurately manipulate the states of multiple spin qubits or transmons. By employing both analytical and simulation techniques, the detailed electrical specifications of the controller have been derived for a single-qubit gate fidelity of 99.99% and validated using a qubit Hamiltonian simulator. Trade-offs between several architectures with different levels of digitization are discussed, resulting in the selection of a highly digital DDS-based solution. Initiating from the system specifications, a complete error budget for the various analog and digital circuit blocks is drafted and their detailed electrical specifications, such as signal power, linearity, spurs and noise, are derived to obtain a digital-intensive power-optimized multi-qubit controller. A power consumption estimate demonstrates the feasibility of such a system in a nanometer CMOS technology node. Finally, application examples, including qubit calibration and multi-qubit excitation, are simulated with the proposed controller to demonstrate its efficacy. The proposed methodology, and more specifically, the proposed error budget lay the foundations for the design of a scalable electronic controller enabling large-scale quantum computers with practical applications.

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Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) and their performance is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the electronics required to interface such large-scale processor is just as relevant and arduous. This paper discusses the challenges in designing a scalable electronic interface for quantum processors. To that end, we discuss the requirements dictated by different qubit technologies and present existing implementations of the electronic interface. The limitations in scaling up such state-of-the-art implementations are analyzed, and possible solutions to overcome those hurdles are reviewed. The benefits offered by operating the electronic interface at cryogenic temperatures in close proximity to the low-temperature qubits are discussed. Although several significant challenges must still be faced by researchers in the field of cryogenic control for quantum processors, a cryogenic electronic interface appears the viable solution to enable large-scale quantum computers able to address world-changing computational problems.

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A quantum computer comprises a quantum processor and the associated control electronics used to manipulate the qubits at the core of a quantum processor. CMOS circuits placed close to the quantum bits and operating at cryogenic temperatures offer the best solution for the control of millions of qubits. The performance requirements of the electronics are very stringent and its design requires the simultaneous optimization of both the circuits and the quantum system. This paper presents the SPINE (SPIN Emulator) toolset for the co-design and co-optimization of electronic/quantum systems. It comprises a SPICE simulator enhanced with a Verilog-A model based on a Hamiltonian solver emulating the quantum behavior of single-electron spin qubits. A co-design methodology is proposed to derive on the one hand the specifications of the electrical signals to be applied to and captured from the qubits, and to ensure on the other hand, the compliance of the electronics in generating the required signals. This methodology results in an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity and cost as proven by a practical design example.@en

Quantum computers have gained widespread interest as they can potentially solve problems that are intractable even for today’s supercomputers, such as the simulation of quantum systems as initially proposed by Feynman. To achieve such tremendous progress, a quantum computer relies on processing the information stored in quantum bits (qubits), the fundamental units of quantum computation, similar to the bits in a classical (i.e., non-quantum) processor. In general, a quantum processor comprising several qubits is connected through a quantum-to-classical interface consisting of classical electrical circuits for manipulating and reading out their quantum state. The accuracy of an operation on a qubit is characterized using the fidelity, which is 100 % in case of a perfect operation. In practice, a fidelity between 99 % and 99.9 % is typically achieved in today’s experiments with less than 100 qubits, limited by non-idealities in the control signals and by the implementation of the physical qubit itself. Since such qubit fidelities are too low to execute relevant quantum algorithms, quantum error correction schemes have been developed which rely on a much larger number of qubits to correct for possible errors, resulting in the need for quantum processors with thousands or millions of qubits. Solid-state qubits promise the largescale integration required to scale to millions of qubits, as they exploit the lithographic fabrication techniques borrowed from the semiconductor industry. However, state-of-theart solid-state qubits, such as transmons and single-electron spin qubits, must be typically cooled to cryogenic temperatures in a dilution refrigerator to exhibit quantum behavior. Because of the limited number of qubits (< 100) in state-of-theart solid-state quantum processors, the classical controller is currently implemented by general-purpose instruments or by tailor-made controllers operating at room temperature connected via several wires to the qubits in the cryogenic chamber. However, these systems must scale to support millions of qubits. While scaling up the underlying quantum processor is already exceptionally challenging, building the electronics required to interface such a large-scale processor is just as relevant and arduous. @en

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.@en

CMOS circuits operating at cryogenic temperature (cryo-CMOS) are required in several lowerature applications. A compelling example is the electronic interface for quantum processors, which must reside very close to the cryogenic quantum devices it serves, and hence operate at the same temperature, so as to enable practical large-scale quantum computers. Such cryo-CMOS circuits must achieve extremely high performance while dissipating minimum power to be compatible with existing cryogenic refrigerators. These requirements asks for cryo-CMOS electronics on par with or even exceeding their roomerature counterparts. This paper overviews the challenges and the opportunities in designing cryo-CMOS circuits, with a focus on analog and mixed-signal circuits, such as voltage references and data converters.

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Quantum computing holds the promise to achieve unprecedented computation power and to solve problems today intractable. State-of-the-art quantum processors consist of arrays of quantum bits (qubits) operating at a very low base temperature, typically a few tens of mK, as shown in Fig. 15.5.1 The qubit states degrade naturally after a certain time, upon loss of quantum coherence. For proper operation, an error-correcting loop must be implemented by a classical controller, which, in addition of handling execution of a quantum algorithm, reads the qubit state and performs the required corrections. However, while few qubits (∼10) in today's quantum processors can be easily connected to a room-temperature controller, it appears extremely challenging, if not impossible, to manage the thousands of qubits required in practical quantum algorithms [1].

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Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.

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A quantum computer fundamentally comprises a quantum processor and a classical controller. The classical electronic controller is used to correct and manipulate the qubits, the core components of a quantum processor. To enable quantum computers scalable to millions of qubits, as required in practical applications, the simultaneous optimization of both the classical electronic and quantum systems is needed. In this paper, a co-design methodology is proposed for obtaining an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity, and cost. The SPINE (SPIN Emulator) toolset is introduced for the co-design and co-optimization of electronic/quantum systems. It comprises a circuit simulator enhanced with a Verilog-A model emulating the quantum behavior of single-electron spin qubits. Design examples show the effectiveness of the proposed methodology in the optimization, design and verification of a whole electronic/quantum system.

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One of the main bottlenecks in the pursuit of a large-scale-chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional array with about 12μm pitch, we create space to implement locally integrated sample-and-hold circuits. This allows us to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling, leading to a Rent's exponent as low as p=0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit array. This work presents a complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and identifying remaining challenges for achieving full fault-tolerant quantum computation. It thereby significantly closes the gap towards a fully CMOS-compatible quantum computer implementation.

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Quantum processors rely on classical electronic controllers to manipulate and read out the state of quantum bits (qubits). As the performance of the quantum processor improves, nonidealities in the classical controller can become the performance bottleneck for the whole quantum computer. To prevent such limitation, this paper presents a systematic study of the impact of the classical electrical signals on the qubit fidelity. All operations, i.e., single-qubit rotations, two-qubit gates, and readout, are considered, in the presence of errors in the control electronics, such as static, dynamic, systematic, and random errors. Although the presented study could be extended to any qubit technology, it currently focuses on single-electron spin qubits, because of several advantages, such as purely electrical control and long coherence times, and for their potential for large-scale integration. As a result of this study, detailed electrical specifications for the classical control electronics for a given qubit fidelity can be derived. We also discuss how qubit fidelity is affected by the limited performance of the general-purpose room-temperature equipment typically employed to control the few qubits available today. Ultimately, we show that tailor-made electronic controllers can achieve significantly lower power, cost, and size, as required to support the scaling up of quantum computers.@en

Cryogenic CMOS (cryo-CMOS) is a viable technology for the control interface of the large-scale quantum computers able to address non-trivial problems. In this paper, we demonstrate state-of-the-art cryo-CMOS circuits and systems for such application and we discuss the challenges still to be faced on the path towards practical quantum computers.@en

Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.@en

Quantum computers (QC), comprising qubits and a classical controller, can provide exponential speed-up in solving certain problems. Among solid-state qubits, transmons and spin-qubits are the most promising, operating « 1K. A qubit can be implemented in a physical system with two distinct energy levels representing the |0) and |1) states, e.g. the up and down spin states of an electron. The qubit states can be manipulated with microwave pulses, whose frequency f matches the energy level spacing E = hf (Fig. 19.1.1). For transmons, f 6GHz, for spin qubits f20GHz, with the desire to lower it in the future. Qubit operations can be represented as rotations in the Bloch sphere. The rotation axis is set by the phase of the microwave signal relative to the qubit phase, which must be tracked for coherent operations. The pulse amplitude and duration determine the rotation angle. A π-rotation is typically obtained using a 50ns Gaussian pulse for transmons and a 500ns rectangular pulse for spin qubits with powers of -60dBm and -45dBm, respectively.

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Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <100 mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.@en

The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.

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