A sparse spin qubit array with integrated control electronics

Conference paper (2019)

Authors

J.M. Boter QCD/Vandersypen Lab - QuTech Advanced Research Centre , QuTech Advanced Research Centre, Kavli institute of nanoscience Delft
J.P. Dehollain Lorenzana QCD/Vandersypen Lab - QuTech Advanced Research Centre , QuTech Advanced Research Centre, Kavli institute of nanoscience Delft
J.P.G. van Dijk Kavli institute of nanoscience Delft, QuTech Advanced Research Centre, OLD QCD/Charbon Lab
T. Hensgens QuTech Advanced Research Centre, Kavli institute of nanoscience Delft, QCD/Vandersypen Lab - QuTech Advanced Research Centre
R. Versluis QuTech Advanced Research Centre, TNO, BUS/General
James S. Clarke Kavli institute of nanoscience Delft
M. Veldhorst QCD/Veldhorst Lab - QuTech Advanced Research Centre , QuTech Advanced Research Centre, Kavli institute of nanoscience Delft
F. Sebastiano QuTech Advanced Research Centre, (OLD)Applied Quantum Architectures
L.M.K. Vandersypen QuTech Advanced Research Centre, QCD/Vandersypen Lab - QuTech Advanced Research Centre , Intel Labs, Kavli institute of nanoscience Delft, QN/Vandersypen Lab - AS
Research Group
QCD/Vandersypen Lab (QuTech Advanced Research Centre) (TU Delft)
Copyright: © 2019 J.M. Boter, J.P. Dehollain Lorenzana, J.P.G. van Dijk, T. Hensgens, R. Versluis, J. S. Clarke, M. Veldhorst, F. Sebastiano, L.M.K. Vandersypen
DOI
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https://doi.org/10.1109/IEDM19573.2019.8993570
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Published Date

2019

Language

English

Reuse Rights

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Faculty

QuTech Advanced Research Centre

Department

Quantum Computing Division

Research Group

QCD/Vandersypen Lab

Abstract

Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.