Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures

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Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures

Conference Paper (2018)

Author(s)

P. A. T'Hart (TU Delft - OLD QCD/Charbon Lab)

J.P.G. van Dijk (TU Delft - OLD QCD/Charbon Lab)

M. Babaie (TU Delft - Electrical Engineering, Mathematics and Computer Science)

E. Charbon (École Polytechnique Fédérale de Lausanne, Intel Corporation)

A. Vladimircscu (ISEP, TU Delft - OLD QCD/Charbon Lab, University of California)

F. Sebastiano (TU Delft - (OLD)Applied Quantum Architectures, Kavli institute of nanoscience Delft)

Research Group

OLD QCD/Charbon Lab

DOI related publication

https://doi.org/10.1109/ESSDERC.2018.8486859 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:3e02a74f-a522-4ae9-88f0-00590be33c43

More Info

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Publication Year

2018

Language

English

Research Group

OLD QCD/Charbon Lab

Volume number

2018-September

Article number

8486859

Pages (from-to)

246-249

Publisher

Editions Frontieres

ISBN (electronic)

9781538654019

Event

48th European Solid-State Device Research Conference, ESSDERC 2018 (2018-09-03 - 2018-09-06), Dresden, Germany

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Abstract

The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.