Characterization and model validation of mismatch in nanometer CMOS at cryogenic temperatures

Conference paper (2018)

Authors

P.A. 't Hart OLD QCD/Charbon Lab
J.P.G. van Dijk OLD QCD/Charbon Lab
M. Babaie Electronics - EEMCS
E. Charbon-Iwasaki-Charbon Swiss Federal Institute of Technology, Intel Labs
A. Vladimirescu OLD QCD/Charbon Lab , ISEP, University of California
F. Sebastiano Kavli institute of nanoscience Delft, (OLD)Applied Quantum Architectures
Research Group
OLD QCD/Charbon Lab
More Info
expand_more

Published Date

2018

Language

English

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Research Group

OLD QCD/Charbon Lab

Abstract

The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.