Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control

Journal Article (2020)
Author(s)

Jeroen P.G. Van Dijk (TU Delft - QuTech Advanced Research Centre, TU Delft - (OLD)Applied Quantum Architectures, TU Delft - OLD QCD/Charbon Lab)

Bishnu Patra (TU Delft - QuTech Advanced Research Centre, TU Delft - OLD QCD/Charbon Lab, Kavli institute of nanoscience Delft)

Stefano Pellerano (Intel Corporation)

Edoardo Charbon (École Polytechnique Fédérale de Lausanne, TU Delft - OLD QCD/Charbon Lab, Kavli institute of nanoscience Delft, TU Delft - (OLD)Applied Quantum Architectures)

Fabio Sebastiano (TU Delft - (OLD)Applied Quantum Architectures, TU Delft - QuTech Advanced Research Centre)

Masoud Babaie (Kavli institute of nanoscience Delft, TU Delft - Electrical Engineering, Mathematics and Computer Science, TU Delft - QuTech Advanced Research Centre)

Research Institute
QuTech Advanced Research Centre
DOI related publication
https://doi.org/10.1109/TCSI.2020.3019413 Final published version
More Info
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Publication Year
2020
Language
English
Research Institute
QuTech Advanced Research Centre
Journal title
IEEE Transactions on Circuits and Systems I: Regular Papers
Issue number
12
Volume number
67
Article number
9189938
Pages (from-to)
5380-5393
Downloads counter
303
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Abstract

The design of a large-scale quantum computer requires co-optimization of both the quantum bits (qubits) and their control electronics. This work presents the first systematic design of such a controller to simultaneously and accurately manipulate the states of multiple spin qubits or transmons. By employing both analytical and simulation techniques, the detailed electrical specifications of the controller have been derived for a single-qubit gate fidelity of 99.99% and validated using a qubit Hamiltonian simulator. Trade-offs between several architectures with different levels of digitization are discussed, resulting in the selection of a highly digital DDS-based solution. Initiating from the system specifications, a complete error budget for the various analog and digital circuit blocks is drafted and their detailed electrical specifications, such as signal power, linearity, spurs and noise, are derived to obtain a digital-intensive power-optimized multi-qubit controller. A power consumption estimate demonstrates the feasibility of such a system in a nanometer CMOS technology node. Finally, application examples, including qubit calibration and multi-qubit excitation, are simulated with the proposed controller to demonstrate its efficacy. The proposed methodology, and more specifically, the proposed error budget lay the foundations for the design of a scalable electronic controller enabling large-scale quantum computers with practical applications.