Exploration of SPAD Based CMOS QRNG Designs

Abstract

In today's digital life, security and encryption are becoming more and more important. As random number generators are a fundamental block of security and encryption, it is crucial to guarantee that these devices operate securely. Random numbers are usually generated in two ways; pseudo random number generators (PRNGs) and true random random number generators (TRNGs). PRNGs output a sequence based on a seed and a mathematical function. The deterministic nature of pseudo RNG devices can result in the PRNG not being applicable for all protocols, in which case TRNGs are needed. Almost all strong cryptography requires TRNGs to generate keys. The difference is that these devices instead rely on real world physics in order to generate a random number. The TRNG implementation explored in this thesis makes use of the quantum mechanical properties of photons. TRNGs making use of this principle of elementary quantum mechanical decision making are called quantum random number generators (QRNGs). This source of entropy provided by photons can be extracted by utilizing SPADs. QRNG devices based on SPADs have been made before in different ways, however there are still large grounds undiscovered when concerning SPAD based designs. As SPAD based QRNGs can be completely produced using CMOS technology, a world of possibilities open, including integration with already existing designs. Different aspects of SPAD QRNG designs will be discussed in this thesis; size, speed, hybrid designs and QRNG test-benching. The first part of the exploration focuses on creating an as small as possible QRNG. This resulted in a QRNG design which is as small as just one flip-flop and one SPAD, which is the smallest QRNG at the time of writing to the authors knowledge. Simulations show that the device is able to run up to 25 Mb/s using a SPAD with low deadtime. This device has been produced using 140nm technology by STMicroelectronics. The second part of the exploration, delves into how fast a SPAD based QRNG can be. The main goals here were to make the fastest possible QRNG with good scalability characteristics. This resulted in a design proposition based on the difference in the time of flight of two photons. This design is simulated using Matlab, and can reach 70 Mb/s per SPAD-duo depending on the deadtime of the SPAD used. When using a SPAD with a deadtime of 1us, the scaled up design needs only 16% of the SPADS needed by a state-of-the-art SPAD based QRNG design based on simulations. The amount of SPADs needed however schales almost linearly with a lower deadtime, having the potential to need only a fraction of the SPADs needed by the state-of-the-art in order to reach the same speeds. Then the concept of hybrid devices is explored, making use of a combination of PRNG and QRNG systems. The first hybrid design proposed is a design in which a very small QRNG is used to generate the key for multiple secure PRNG systems. The PRNG system used in this design is a trivium stream cypher. The design is completely written in VHDL except for the external QRNG. It then has been compiled and simulated using ModelSim, again using 140nm technology by STMicroelectronics. This resulted in a design which is able to reach speeds of 640 Gb/s, while using a total area of 99936 um2. The second hybrid device proposes a LFSR based design, which makes use of multiple very small QRNG devices to influence the function that the LFSR implements in order to increase the security. The last part of the exploration explores how it can be made easier and faster to test QRNG designs in an early design stage more accurately. As the source of entropy is quantum, the only risk of affecting the randomness is purely in which form the data of the photons is processed. By creating a chip which is able to extract the time of flight and the exact location of where the photon hit, testing potential QRNG devices can already be done in an early design stage with real-time data. A part of the chip that measures the time of flight of the photons arriving, has been designed in 40nm technology by STMicroelectronics. This part is a novel counter based on the principle of Gray counting, and is simulated extensively using extracted layout simulations. These simulations show that the device is able to run at speeds up to 3.6 GHz.