As technology is scaling down by reducing the lateral and vertical dimensions of transistors. It becomes necessary to reduce the supply voltage, enhancing lower power dissipation and to maintain device reliability. This scaling makes the digitally controlled oscillator (DCO) more susceptible to interference between systems on the chip (SoC). For instance, the coupling from the power amplifier(PA) leads to injection pulling of the DCO. Especially in the non-constant envelope modulation schemes, e.g. π/4-DQPSK and DQPSK, the frequency pulling is extremely troublesome causing severe disrupted output spectrum. Now that Bluetooth provides, besides the Bluetooth Basic Rate(BR) also Enhanced Data Rate (EDR) and Bluetooth Low Energy(BLE) a radio with multiple purposes becomes more complex. Especially in the case where EDR uses π/4-DQPSK or DQPSK and the BLE only GFSK modulation. Therefore, in this thesis a dual frequency DCO at 4.8GHz and 9.6GHz is designed to mitigate the coupling issues with the PA. It also includes a study in AM-FM, where an optimal amplitude of oscillation shows minimal variation of frequency. An overall low power is maintained at 1V supply and a current of 308μA and 765μA for BLE and EDR respectively. Moreover, the thesis shows an attempt to leave out the Low Dropout Regulator to address future scaling challenges ahead. The DCO is simulated in 22nm-FDSOI occupying a core area of 0.0543 mm2 and achieves a Phase Noise of -116 dBc/Hz after dividing the frequencies 5.06 GHz and 10.74 GHz into the 2.4 GHz band

Quadrature clocks have been widely used in both wireless and wireline communication systems. This Master’s project presents a quadrature clock generator operating in the 10 GHz to 20 GHz range, specifically tailored for quantum computing applications. The design utilizes delay lines to generate quadrature clocks, ensuring low phase noise. To control the delay of these lines, the delay difference is extracted by down-converting the high-frequency signal (10-20 GHz) to a baseband frequency (50 MHz) while retaining the phase difference. Quadrature errors are detected using a tunable delay line and a bang-bang phase detector, resulting in a design that is immune to static delay variations between the two delay extraction paths and is power efficient.

The escalating demand for higher data rates in modern communication networks are pushing more transmitters and receivers to use a modulation technique with more spectral efficiency, like pulse amplitude modulation 4-level (PAM-4).

On the receiver side, phase detection for PAM-4 has proven to be difficult with most receivers using phase detection for non return to zero (NRZ) data. This neglects most transitions and thus some phase information is lost. This results in low bandwidth and jitter tolerance, which is a problem in noisy communication systems where it will lead to a high bit error rate (BER).

This thesis explores an integrated PAM-4 clock and data recovery (CDR) circuit utilizing a novel PAM-4 bang bang phase detector (BBPD) considering all data transitions. A digital oscillator with variable gain is used in order to achieve high jitter tolerance as-well as low jitter generation. at 24Gb/s the CDR consumes 8mW and generates 487fs of jitter. and has a 1UI at 30MHz.

Quantum computers promise large speedups compared to classical computers for specific classes of problems by exploiting quantum phenomena for computation. Despite notable progress towards larger systems, today's quantum computers still lack the necessary size for realizing many of the anticipated benefits. Scaling to these larger numbers is complicated by the fragility of the qubits, which raises the necessity of operating the quantum computing core at deep cryogenic temperatures to limit the influence of noise. However, in the present experimental setups for quantum computing the electronic interfaces are often based on equipment operated at room temperature. This arrangement creates a potential wiring bottleneck towards cryogenic temperature, that is connected to reliability limitations. A proposed solution to this challenge is moving the interfacing electronics close to the qubits into the cryogenic environment. However, implementation of the electronics at cryogenic temperature places a set of system constraints that prevents directly porting the room-temperature electronics. The most prominent of these constraints is the limited cooling power at deep cryogenic temperature, requiring the interfacing electronics to save power wherever possible. To implement the necessary functions of the interface in practice, CMOS technology is uniquely positioned due to its large scale integration capabilities, low-power digital logic and sustained performance at cryogenic temperature.

In this work, contributions to the readout electronics of quantum computers are made, with an emphasis on the readout of semiconductor spin quantum computers. Readout poses a significant challenge for current spin-qubit systems, especially its scalable integration into the electronic interface. This dissertation can be separated into contributions to the readout of quantum computers in three main categories: cryogenic digitization, cryogenic noise characterization and readout benchmarking.

The wide-band signals present in the frequency-multiplexed RF readout interface require corresponding wide-band digitization capabilities of the associated data converters. In this work, we present robust, power-efficient and high-speed time-interleaved SAR ADC designs adopted to operation at cryogenic temperature to serve this application. These include the first high-speed cryo-CMOS SAR ADC suitable for operation in the RF readout interface, further efficiency improvements to this ADC and finally an ADC tightly integrated with an efficient body-bias enabled dynamic pre-amplifier. The body-bias enabled pre-amplifier also demonstrated excellent room-temperature performance, with the best reported combined power efficiency of a high-speed SAR and driver circuit.
All designs have been realized in a 40nm CMOS technology and characterized at cryogenic temperature.

For the directed design of many of the functions in the electronic interface, accurate models for simulation are required. While significant work has been presented on DC characterization at cryogenic temperatures, comparatively little work covering low-frequency noise is available. To help further development, an extensive low-frequency noise characterization is performed on a 40nm CMOS technology at cryogenic temperature. The results of this characterization allow a broad overview over the low frequency noise behavior of the technology. Given the radical change in temperature between room-temperature and cryogenic temperature, a surprisingly small overall change in the input-referred noise is observed. The most prominent difference is the finding of a systematic Lorentzian feature at cryogenic temperature that is for the first time described here.

Lastly, while promising designs have been suggested for the DC-readout of spin qubits, guidelines for directing such designs have been lacking. In order to provide a set of such guidelines, we first demonstrate that the limits of DC-readout lie significantly beyond current state-of-the-art, with much room for improvement on the electronics. Then, we analyze the voltage amplifier, the transimpedance amplifier, the charge sampling, and the current pre-amplifier by deriving their design equations and trade-offs.
Finally the various architectures are compared with the fundamental limit and suggestions for specific use-cases are give. The results suggest that DC-readout is a promising path for the development of a scalable spin-qubit readout.@en

The current trend in the state-of-the-art oscillators achieves low phase noise performance. Such stringent performance is demanded in modern Communication Systems. This thesis proposes the design of a CMOS oscillator achieving the ultra-low phase noise. This design is based on TSMC 40 nm technology, the supply voltage is 1.1 V, and the oscillation frequency is f_start=6.65 GHz and f_stop=7.58 GHz, the tuning range is calculated to be 13 % with the Phase Noise@ 1 MHz(normalized to 10 GHz) varies from -128.1 dBc/Hz to -130.4 dBc/Hz and Figure of Merit varies from 188.0 dBc/Hz to 190.0 dBc/Hz, consuming average power of 95 mW and the f_corner is 250 kHz. Since the chip is still in fabrication and the final result only includes the simulation result. Further work involves the measurement and performance validation.

Transmit digital-to-analog converters have become an essential building block for state-of-the-art Ethernet infrastructures. They are also one of the most significant sources of power consumption in an Ethernet physical layer (PHY) transceiver. These devices must maintain high linearity and a well-defined impedance of 100 Ω while operating at a speed of several GS/s. This thesis investigates the resistive digital-to-analog converter architecture, which is inherently more power-efficient than the widely used current-steering architecture. A technique to linearize the supply current, which reduces distortion caused by finite supply impedance, is proposed. The resulting 12-bit DAC designed in 180nm technology maintains INL and DNL error of +-0.6 LSB on a 12-bit level across temperature (-40 to 150°C) and corners. The DAC operates with a clock speed of 200 MS/s, achieving IM3 >85 dB at low frequency.

Reducing power consumption is becoming increasingly important for the sustainability of the communication industry because it is expected to consume a significant portion of the global electricity in the face of the exponentially increasing demands on the volume and rate of data transmission. As the scope narrows to the individual wireless device level, the reduced power consumption helps to extend the lifetime of battery-powered devices, thereby leading to improved user experience and enabling the development of innovative applications. The quest for the lower power consumption will profoundly shape the wireless transceiver design, i.e., each critical block in the system should constantly reduce its drained power without sacrificing the performance. With this background, the thesis focuses on the phase-locked loops (PLL) that generate RF clocks for wireless transceivers, and develops low-power techniques suppressing the fractional-spur levels when the PLL generates unmodulated carrier, and the phase modulation (PM) error when the PLL additionally serves as a two-point modulator...@en

Receivers for millimeter-wave (mm-wave) 5G, with the ability to detect a low-power desired signal, in the vicinity of large power blockers, require highly linear circuitry with a large power consumption. Suppressing the out-of-band blockers reduces this power consumption. N-path filters (NPFs) have recently been used to reject interferers in adjacent channels, by using a tunable center frequency. The state-of-the-art NPFs at mm-wave, however, only have a limited attenuation or use a large chip area. In this thesis, a fourth-order NPF is designed for 26-30 GHz. The implemented filter combines two frequency-shifted NPFs to create a flat in-band response and a steep roll-off, without the use of a large passive baseband filter. A rejection of 14 dB in the center of the first adjacent channel is obtained. This increases up to 24 dB at far-out-of-band frequencies. The noise figure of 10-12 dB is the lowest of the state-of-the-art, due to the added low-noise amplifier (LNA) in front of the filter. Despite this LNA, the designed filter achieves a comparable power consumption (40 mW) and smaller area (0.2-0.3 µm) than the state-of-the-art. The filter designed in this thesis is the first reported active N-path filter at mm-wave. The bandwidth is among the smallest reported, while the estimated area is lower than the state-of-the-art.

Phase-locked loops (PLLs) are ubiquitous in many RF applications such as frequency synthesizers in wireline and wireless transceivers. In this project, a charge-sampling PLL has been designed, which employs a charge-domain sub-sampling phase detector. The high gain of the phase detector helps suppress the in-band phase noise, while the lowered duty cycle of the sampling reference clock results in reduced reference spurs. A current-starved ring oscillator has been designed to support an output frequency range of 1-2 GHz. In order to achieve the synthesis of fractional frequencies, a capacitive DAC based constant slope digital-to-time converter (DTC) has been designed. In order to calibrate the DTC gain (KDTC) over PVT variations, a digital background gain calibration loop has been introduced. The performance of the Fractional-N PLL is comparable to that of the state-of-the-art. In order to measure the PLL's performance in silicon, the design has been taped-out in TSMC 40-nm technology in July 2022.

A key issue in current quantum computing interfaces is the dense interconnect between electronics at cryogenic temperature (CT) and room temperature (RT). Recently, progress has been made to move more control electronics from RT to CT, reducing interconnect overhead. The next step towards minimal interconnect is a direct wireline interface between RT and CT. This work presents a full­rate 10 Gb/s clock­and­data recovery circuit for a high speed serial link receiver operating at CT.

A novel phase detector is utilized to reduce power consumption by removing the need for both a pulse generator at the input and, a buffer between the phase detector and voltage controlled oscillator. Additionally, a digital delay­locked loop is added to improve the retiming margin, achieving higher jitter tolerance. Implemented in 40­nm CMOS, post­layout simulation shows a core power consumption of 3.89 mW from a 1.1­V supply at 10 Gb/s, producing an rms­jitter of 84 fs and an estimated jitter tolerance
of 1.1 UIpp at 10 MHz.

With the emergence of new communication standards like Fifth-­Generation New Radio (5G NR), technologies are being developed to exploit millimeter­ wave (mm-­wave) frequency bands from 30­300 GHz, for their advantage of high bandwidth availability. Generation of carrier frequencies for these mm-­wave applications imposes a challenging specification of high spectral­ purity on the frequency synthesizers. Sub­sampling PLLs (SSPLLs) show a remarkable performance in terms of low­ power and good spectral purity, which are critical for such high­speed applications. However, due to their low lock­-in range, SSPLLs require the assistance of an additional frequency­-tracking loop (FTL) for an improved locking performance. These FTLs conventionally employ either high power consuming frequency dividers, or reference frequency multipliers. In this thesis, a novel implementation of an FTL which avoids the usage of high-­frequency dividers is proposed. The proposed FTL uses three sub­-Nyquist sampling rates, which are derived from three mutually co­prime integers, for an unambiguous VCO frequency estimation which helps in frequency error correction. Consequently, the proposed FTL eliminates the need of sampling rates higher than the Nyquist rate and the circuit limitations posed by such high sampling frequencies. The FTL employs a simple amplifier, counter and look­up table based VCO frequency estimation procedure which avoids the need of performing high complexity frequency estimation algorithms like Fast Fourier Transform (FFT). The FTL also features a speed optimization algorithm which helps in achieving low frequency­-locking times. The proposed FTL is designed in the 40­nm CMOS technology, targeting an output frequency locking range of 9.8­12.2 GHz. The post-­layout simulations show that the FTL is able to coarsely lock to any desired frequency in the wide­band locking range within an error of 3 MHz, in less than 3 휇s at start-up. Error injections as high as 1.5 GHz are efficiently detected and corrected in less than 3 휇s as well. The area consumed by the FTL is 0.35 푚푚2 and the active area of the total chip is 1.09 푚푚2 including the decoupling capacitors. The FTL consumes a maximum power of 1.56 mW when the PLL is in a locked state. A comparison with other state-­of-­the-­art frequency­-tracking loops demonstrates its clear advantage of wide­band frequency locking and low locking time, while consuming a similar amount of power. Analytically, the proposed FTL also exhibits competence in scaling to mm­wave frequencies.

With the current advancements in quantum computing moving more circuitry into the cryogenic chamber there is a need for high-speed connectivity between the cryogenic and room temperature environment. Studies conducted to date have achieved high-speed links of multiple Gb/s utilizing a single CMOS chip at room temperature, yet a Cryo-CMOS wireline transmitter addresses a new topic in high-speed cryogenic electronic design necessary for the functioning and scale-up of quantum computers. This thesis entails the design of A DAC-based Cryo-CMOS 51.2 Gb/s PAM4 Wireline Transmitter. Overall, the proposed design is meant to demonstrate a high-speed signal generated by a Cyro-CMOS chip can be send through a cable from a cryogenic environment and received at room temperature. Requirements have been set up based on the measurement of the cable channel and simulation results showed these could be met with the designed circuitry. The system consists of a low-speed 16-to-1 serializing structure, a high-speed 4-to-1 Multiplexer, and a 6-bit (4b binary, 2b unary) CML DAC. The design is finished and taped out in 40-nm technology, however the chip is still in fabrication, so the results are based on simulation data only, in future research measurements will verify the working of the chip.

This report describes the design of different amplifiers that are part of an FM transceiver. This is part of a larger project, which has the objective to design a complete FM transceiver from discrete components only, meaning that IC technology is not considered.
The circuits designed are two baseband amplifiers, an intermediate frequency amplifier, a low noise amplifier and an RF power amplifier. The baseband amplifiers are implemented with a Darlington pair in common-collector configuration to achieve a high input resistance, low output resistance, and unity gain transfer.
The intermediate frequency amplifier is centered at 9.95 MHz with a -3dB bandwidth of 2 MHz. The maximum gain is 40.5 dB and can be lowered with up to 39.7 dB using a potentiometer, based on the emitter degeneration principle.
The low noise amplifier has a maximum noise figure of 1.4 dB over the RF carrier band of 88 to 108 MHz. It has a gain of 33 dB, and reaches its 1 dB compression point for an input of -33 dBm. The total harmonic distortion is less than 0.3%.
A class E power amplifier is designed with an efficiency of 72.9%, a transmit power of 3.1 W, and a gain of 31.8 dB.
Furthermore, this reports also presents a systematic design approach for amplifiers, which illustrate the core principles on which all the designs are based.

IoT refers to a network of connected devices that exchange data for different applications using different wireless standards such as Cellular, ZigBee, Bluetooth, Mesh Networks, and the widely used WiFi. For IoT applications that do not require high data rates but require long-range data transmission and low power operation, a sub 1GHz WiFi standard - 802.11ah - was introduced. This thesis focuses on implementing a low power receiver design for IoT application. A reconfigurable zero-IF (ZIF)/ low-IF (LIF) architecture is designed to support the 802.11ah specifications. In the implemented SAW-less receiver design, the input RF signal is directly downconverted by mixing operation to baseband frequencies by current-mode passive mixers. The baseband provides the required selectivity and sensitivity of the system. The receiver provides a 24 – 44 dB programmable gain across 1,2,4 MHz bandwidth. It supports an ACR/NACR of 17 dB/32 dB with an overall power consumption of 4 mW at 6 dB NF. The designed receiver is implemented in TSMC 40 nm and is in the fabrication process.

Quantum computers hold a promise to solve intractable problems that can not be solved with classical computers. In quantum computers, information is processed in qubits as opposed to bits. The proper operation of qubits requires them to be operated in a quantum state; hence they need to be cooled down to temperatures well below <1K. Using qubits and their quantum mechanical property, quantum computers can achieve exponential speedup in solving certain computing problems compared to classical computers. However, this can only be achieved by employing thousands of qubits. At the current state of play, quantum computers are still far from practical. The current state-of-the-art solution dictates that each qubit needs multiple interconnects towards room temperature and requires bulky room temperature instruments for qubit readout and control. Clearly, this current solution will not scale well for a quantum computer with many qubits. In an effort to solve this issue, it has been proposed to realize dedicated integrated circuits for control and readout of the qubits and operate them closer to the qubits' operating temperature to enable scalability.
The thesis presents the implementation of an integrated RF receiver for spin and superconducting qubit readout applications. The work aims to replace the bulky room temperature electronics with an integrated solution that operates at 4K to enable scalability and simplification of the quantum computing architecture. The receiver has been designed in the TSMC 40nm CMOS technology and has been characterized in room temperature and 4K. The measured performance shows that the receiver features a gain of 58 dB and a minimum double-sideband noise figure of 0.6 dB at 4K with an operating frequency of 6-8 GHz; a comparable performance to the current state-of-the-art room temperature electronics used for qubit readout. Moreover, this work demonstrates a qubit readout experiment with the integrated receiver in both room temperature and 4K. The qubit readout experiment shows a comparable qubit readout performance with the integrated receiver at room temperature. However, due to oscillation problems, a degradation in qubit readout performance with the chip operating at 4K is observed.

In this bachelor thesis the design process of the audio and intermediate frequency amplifiers for a wireless FM tranceiver is documented and explained. The project was done using only descrete components for educational purposes.

This report details the design and implementation of subsystems within a wireless FM transceiver. All the subsystems will be developed and integrated into a working FM transceiver. The subsystems discussed in this report are the modulator and demodulator. The modulator, on the transmitter side, varies the carrier wave frequency, based on the input audio signal. The demodulator, on the receiver side, can detect these variations and retrieve the audio signal. The modulator is implemented using a voltage controlled oscillator, which is based on the Colpitts oscillator. The input audio signal controls the oscillation frequency by modulating varicaps. The demodulator consists of mixer, amplifier and a slope detector. The amplifier is not discussed in this thesis. The mixer uses a local oscillator to shift the RF input signal to an intermediate frequency. This thesis proposes a mixer integrated into a local oscillator, using only one transistor. The detector is based on a slope detector, which differentiates the FM signal and converts it into an AM signal. The differentiator is implemented using a bandpass filter. The audio signal is retrieved from the AM signal using an envelope detector. The work will be concluded with a display of the complete FM transceiver circuit.

This thesis explains the design process of two subsystems of a radio transmitter and receiver. The goal of the project is to transmit audio over a distance using FM modulation. This report will focus on the power amplifier leading to the transmitting antenna and the low noise amplifier connected to the receiving antenna. A design process for a class E power amplifier and a low noise amplifier will be discussed.

The communication standard IEEE802.11ah, also known as Wifi Halow, is developed especially for IoT applications. This standard works in the sub-GHz range and can, therefore, offer a longer transmission range and achieve low power consumption. This makes the standard suitable for IoT applications. In this thesis, a Low Noise Transconductance Amplifier (LNTA) for an IEEE802.11ah receiver is designed. The LNTA has a single voltage input and a differential current output and is designed in the TSMC 40nm technology. The LNTA will be low power and suit the whole IEEE802.11ah frequency band, while also meeting the specifications on noise figure, input matching and linearity and having several gain settings. In the first stage, the transconductance is boosted to reduce the current consumption and still meet the input matching condition. The second stage of the LNTA provides the single to differential conversion. A detailed description of the design steps is discussed in this thesis.