Resistor-Based Digital-to-Analog Converters

Master Thesis (2023)
Authors

M.M. Nawrocki (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Supervisors

K. Bult (TU Delft - Electronics)

Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
Copyright
© 2023 Maciej Nawrocki
More Info
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Publication Year
2023
Language
English
Copyright
© 2023 Maciej Nawrocki
Graduation Date
27-11-2023
Awarding Institution
Delft University of Technology
Programme
Electrical Engineering
Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
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Abstract

Transmit digital-to-analog converters have become an essential building block for state-of-the-art Ethernet infrastructures. They are also one of the most significant sources of power consumption in an Ethernet physical layer (PHY) transceiver. These devices must maintain high linearity and a well-defined impedance of 100 Ω while operating at a speed of several GS/s. This thesis investigates the resistive digital-to-analog converter architecture, which is inherently more power-efficient than the widely used current-steering architecture. A technique to linearize the supply current, which reduces distortion caused by finite supply impedance, is proposed. The resulting 12-bit DAC designed in 180nm technology maintains INL and DNL error of +-0.6 LSB on a 12-bit level across temperature (-40 to 150°C) and corners. The DAC operates with a clock speed of 200 MS/s, achieving IM3 >85 dB at low frequency.

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