A 24Gb/s PAM-4 Clock and Data Recovery Circuit With High Jitter Tolerance

Master thesis (2024)

Authors

J.I. Bas Electrical Engineering, Mathematics and Computer Science

Contributors

M. Babaie Electronics - EEMCS (mentor)
R. Gurbaxani Electronics - EEMCS (coach)
F. Sebastiano Quantum Circuit Architectures and Technology - EEMCS (graduation committee member)
Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
Copyright: © 2024 Ivor Bas
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Published Date

11-03-2024

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

The escalating demand for higher data rates in modern communication networks are pushing more transmitters and receivers to use a modulation technique with more spectral efficiency, like pulse amplitude modulation 4-level (PAM-4).

On the receiver side, phase detection for PAM-4 has proven to be difficult with most receivers using phase detection for non return to zero (NRZ) data. This neglects most transitions and thus some phase information is lost. This results in low bandwidth and jitter tolerance, which is a problem in noisy communication systems where it will lead to a high bit error rate (BER).

This thesis explores an integrated PAM-4 clock and data recovery (CDR) circuit utilizing a novel PAM-4 bang bang phase detector (BBPD) considering all data transitions. A digital oscillator with variable gain is used in order to achieve high jitter tolerance as-well as low jitter generation. at 24Gb/s the CDR consumes 8mW and generates 487fs of jitter. and has a 1UI at 30MHz.