With the emergence of new communication standards like Fifth-­Generation New Radio (5G NR), technologies are being developed to exploit millimeter­ wave (mm-­wave) frequency bands from 30­300 GHz, for their advantage of high bandwidth availability. Generation of carrier frequencies for these mm-­wave applications imposes a challenging specification of high spectral­ purity on the frequency synthesizers. Sub­sampling PLLs (SSPLLs) show a remarkable performance in terms of low­ power and good spectral purity, which are critical for such high­speed applications. However, due to their low lock­-in range, SSPLLs require the assistance of an additional frequency­-tracking loop (FTL) for an improved locking performance. These FTLs conventionally employ either high power consuming frequency dividers, or reference frequency multipliers. In this thesis, a novel implementation of an FTL which avoids the usage of high-­frequency dividers is proposed. The proposed FTL uses three sub­-Nyquist sampling rates, which are derived from three mutually co­prime integers, for an unambiguous VCO frequency estimation which helps in frequency error correction. Consequently, the proposed FTL eliminates the need of sampling rates higher than the Nyquist rate and the circuit limitations posed by such high sampling frequencies. The FTL employs a simple amplifier, counter and look­up table based VCO frequency estimation procedure which avoids the need of performing high complexity frequency estimation algorithms like Fast Fourier Transform (FFT). The FTL also features a speed optimization algorithm which helps in achieving low frequency­-locking times. The proposed FTL is designed in the 40­nm CMOS technology, targeting an output frequency locking range of 9.8­12.2 GHz. The post-­layout simulations show that the FTL is able to coarsely lock to any desired frequency in the wide­band locking range within an error of 3 MHz, in less than 3 휇s at start-up. Error injections as high as 1.5 GHz are efficiently detected and corrected in less than 3 휇s as well. The area consumed by the FTL is 0.35 푚푚2 and the active area of the total chip is 1.09 푚푚2 including the decoupling capacitors. The FTL consumes a maximum power of 1.56 mW when the PLL is in a locked state. A comparison with other state-­of-­the-­art frequency­-tracking loops demonstrates its clear advantage of wide­band frequency locking and low locking time, while consuming a similar amount of power. Analytically, the proposed FTL also exhibits competence in scaling to mm­wave frequencies.